System and method for analyzing defects on a wafer

1. A defect analyzer system, comprising:

a program storage device storing instructions; and

an arithmetic unit executing the instructions to:

divide a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon;

store a pattern feature quantity based on design data of the circuit pattern;

extract a pattern feature quantity for each of the grid squares from the stored pattern feature quantity;

classify the plurality of grid squares into a plurality of groups based on the pattern feature quantities;

store defect information including a defect position and size having been detected in the defect analyzing region;

extract the defect information from the stored defect information and match the defect information with the defect analyzing region;

determine the number of defects for each defect size in each of the plurality of groups and calculate a defect size distribution;

compare the defect size distribution and a predetermined estimation distribution in each of the plurality of groups and calculate a difference; and

compare the difference of each of the plurality of groups and a predetermined threshold value, extract the group having the difference equal to or smaller than the predetermined threshold value, and output the defect information corresponding to the extracted group.

2. The defect analyzer system according to claim 1 , further comprising a defect analyzing unit configured to perform defect analysis using the defect information outputted from the arithmetic unit.

3. The defect analyzer system according to claim 1 , wherein the arithmetic unit executes the instructions to correct a test parameter of a defect tester which tests a defect of the wafer, based on a comparison result of the predetermined estimation distribution and a defect size distribution of a group having not been extracted by the arithmetic unit.

4. The defect analyzer system according to claim 1 , wherein the pattern feature quantity is at least one selected from a pattern coverage factor, a pattern perimeter, and a defect size based on a critical area analysis.

5. A defect analyzing method comprising:

dividing, by an arithmetic unit, a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon;

extracting, by the arithmetic unit, a pattern feature quantity for each of the grid squares based on design data of the circuit pattern;

classifying, by the arithmetic unit, the plurality of grid squares into a plurality of groups based on the pattern feature quantities;

matching, by the arithmetic unit, the defect analyzing region with defect information including a defect position and size having been detected in the defect analyzing region;

determining, by the arithmetic unit, the number of defects for each defect size in each of the plurality of groups and calculating a defect size distribution;

comparing, by the arithmetic unit, the defect size distribution of each of the plurality of groups and a predetermined estimation distribution and calculating a difference;

comparing, by the arithmetic unit, the difference of each of the plurality of groups and a predetermined threshold value and extracting the defect information corresponding to the group having the difference equal to or smaller than the predetermined threshold value; and

performing, by a defect analyzing unit, defect analysis using the extracted defect information.

6. The defect analyzing method according to claim 5 , further comprising correcting, by the arithmetic unit, a test parameter of a defect tester which tests a defect of the wafer, based on a comparison result of the predetermined estimation distribution and a defect size distribution of a group having the difference larger than the predetermined threshold value.

7. The defect analyzing method according to claim 5 , wherein the pattern feature quantity is at least one selected from a pattern coverage factor, a pattern perimeter, and a defect size based on a critical area analysis.

8. A defect analyzer system comprising:

a grogram storage device storing instructions; and

an arithmetic unit executing the instructions to:

divide a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon;

store a pattern feature quantity based on design data of the circuit pattern;

extract a pattern feature quantity for each of the grid squares from the stored pattern feature quantity;

classify the plurality of grid squares into a plurality of groups based on the pattern feature quantities;

store defect information including a defect position and size having been detected in the defect analyzing region;

extract the defect information from the stored defect information and match the defect information with the defect analyzing region;

determine the number of defects for each defect size in each of the plurality of groups and calculate a defect size distribution; and

identify whether the defects in each of the plurality of groups are random defects or systematic defects, based on the defect size distribution.

9. The defect analyzer system according to claim 8 , wherein the arithmetic unit executes the instructions to calculate an approximate function of the defect size distribution and identifies whether the defects are random defects or systematic defects based on a power value of the approximate function.

10. The defect analyzer system according to claim 8 , wherein the arithmetic unit executes the instructions to determine a priority order of defect analysis on the plurality of groups based on an identification result of the defects in each of the plurality of groups, and output the defect information corresponding to the groups according to the priority order.

11. The defect analyzer system according to claim 10 , further comprising a defect analyzing unit configured to perform defect analysis using the defect information outputted from the arithmetic unit.

12. The defect analyzer system according to claim 8 , wherein the pattern feature quantity is at least one selected from a pattern coverage factor, a pattern perimeter, and a defect size based on a critical area analysis.

13. A defect analyzing method comprising:

dividing, by an arithmetic unit, a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon;

extracting, by the arithmetic unit, a pattern feature quantity for each of the grid squares based on design data of the circuit pattern;

classifying, by the arithmetic unit, the plurality of grid squares into a plurality of groups based on the pattern feature quantities;

matching, by the arithmetic unit, the defect analyzing region with defect information including a defect position and size having been detected in the defect analyzing region;

determining, by the arithmetic unit, the number of defects for each defect size in each of the plurality of groups and calculating a defect size distribution;

identifying, by the arithmetic unit, whether the defects in each of the plurality of groups are random defects or systematic defects, based on the defect size distribution;

determining, by the arithmetic unit, a priority order of defect analysis on the plurality of groups based on an identification result and extracting the defect information corresponding to each of the groups according to the priority order; and

performing, by a defect analyzing unit, defect analysis using the extracted defect information.

14. The defect analyzing method according to claim 13 , further comprising calculating, by the arithmetic unit, an approximate function of the defect size distribution and identifying whether the defects are random defects or systematic defects based on a power value of the approximate function.

15. The defect analyzing method according to claim 13 , wherein the pattern feature quantity is at least one selected from a pattern coverage factor, a pattern perimeter, and a defect size based on a critical area analysis.