Semiconductor device including vertical MOS transistors
View Patent ↗A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode ( 2 ) of a first conductivity type; first semiconductor pillars ( 3, 4 and 5 ) with a gate insulating film ( 18 ) formed therearound, across the gate insulating film ( 18 ) the vertical MOS transistors facing the gate electrode; and a second semiconductor pillar ( 8 ) being of the first conductivity type which is the same as the conductivity type of the gate electrode and being in contact with the gate electrode at a portion thereof from which at least a part of the gate insulating film is removed, wherein potential supply ( 6 ) to the shared gate electrode ( 2 ) is effected through the second semiconductor pillar ( 8 ).
1. A semiconductor device comprising:
a plurality of vertical MOS transistors sharing a gate electrode of a first conductivity type, wherein said plurality of vertical MOS transistors comprises first semiconductor pillars with a first gate insulating film formed around lateral sides of the first semiconductor pillars, and the lateral sides of the first semiconductor pillars facing said gate electrode via said first gate insulating film; and
a second semiconductor pillar being of the first conductivity type with a second gate insulating film formed around lateral sides of the second semiconductor pillar, and being in contact with said gate electrode at a portion thereof from which at least a part of said second gate insulating film is removed, wherein potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through said second semiconductor pillar.
2. The semiconductor device according to claim 1 , wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through an electrode/interconnection contacted on the top of said second semiconductor pillar.
3. The semiconductor device according to claim 1 , wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through an electrode/interconnection contacted with a diffusion layer of the first conductivity type formed at the bottom of said second semiconductor pillar.
4. The semiconductor device according to claim 1 , wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected by driving a separate vertical MOS transistor which shares with said second semiconductor pillar a diffusion layer of the first conductivity type formed at the bottom of said second semiconductor pillar.
5. The semiconductor device according to claim 1 , which includes an arrayed configuration wherein: a plurality of transistor columns is disposed each including said plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; and transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
6. The semiconductor device according to claim 2 , which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
7. The semiconductor device according to claim 3 , which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
8. The semiconductor device according to claim 4 , which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.