Circuit used in digitizing analog video from an image pixel array
Disclosed herein is a camera system and camera controller having a modularized design. Camera control functions within the controller are distributed among a number of modules, each module performing a component task of controlling a camera. Individual modules can perform tasks such as generating clock signals, digitizing an analog video signal, and providing multiplexed digital video output. Modules communicate with each other over a common bus sufficient to carry the signals necessary to control the camera. The system implements a RAM-based digital sequencer that provides the capability of loading bit patterns into memory and using these patterns to generate waveforms for clocking a CCD. Clock and readout sequences can be composed in a high level language, compiled and uploaded into the controller. Adjustable clamp and sample signal delays used in digitizing an analog video signal provide the capability to optimize the performance of the system in a given application.
1. A circuit capable of being used in digitizing an analog video signal from an image pixel array comprising:
a filter circuit; and
a filter bypass circuit comprising:
an operational amplifier configured to operate as a switch, the operational amplifier comprising a high speed enable input,
an input side of said switch connected to the input node of said filter circuit,
an output side of said switch connected to the output node of said filter circuit,
wherein the high speed enable input is configured to receive a bypass signal to activate the switch, the switch being capable of closing in response to the bypass signal received by the operational amplifier and of causing the analog video signal to be transmitted through the filter bypass circuit to bypass the filter circuit.
2. A circuit as in claim 1 , wherein said circuit further comprises a connector for coupling the filter circuit and filter bypass circuit to a bus of a modular camera system.
3. A circuit as in claim 1 , wherein the filter circuit and filter bypass circuit are configured for connection to an AC-DC converter submodule to digitize the analog video signal from an image pixel array.
4. A circuit as in claim 1 , wherein the input side of said switch is connected to a first end of a resistor having a second end connected to the non-inverting input of the operational amplifier.
5. A circuit as in claim 4 , wherein an inverting terminal of the operational amplifier is connected to an additional resistor having a second end connected to the output side of the operational amplifier, the output side of the operational amplifier being the output side of said switch.
6. A circuit as in claim 1 , wherein an inverting terminal of the operational amplifier is connected to an additional resistor having a second end connected to the output side of the operational amplifier, the output side of the operational amplifier being the output side of said switch.
7. A circuit as in claim 1 , wherein the operational amplifier has an on-resistance of approximately 10 ohms.
8. An input module for use in a modular camera system which transmits a signal including a plurality of pixels at a selected readout frequency, the input module comprising:
a configurable low pass filter connected to receive the signal including the plurality of pixels, the low pass filter configurable to minimize noise at the selected readout frequency;
a pluggable analog-to-digital converter for digitizing the signal to generate image data;
a filter bypass circuit for bypassing said low pass configurable filter, and
a plug-in connector for connecting the analog-to-digital converter with the configurable low pass filter and the filter bypass circuit.
9. The input module of claim 8 , wherein said input module is configurable to receive a particular bit resolution.
10. The input module of claim 9 , wherein said particular bit resolution is selected to accommodate a particular signal to noise range.
11. The input module of claim 9 , wherein said particular bit resolution is selected to accommodate a particular component shortage.
12. The input module of claim 8 , wherein said submodule may be configured to receive a particular bit speed.
13. The input module of claim 12 , wherein said particular bit resolution is selected to accommodate a particular signal to noise range.
14. The input module of claim 12 , wherein said particular bit resolution is selected to accommodate a particular component shortage.
15. The input module of claim 12 , wherein said submodule is coupled to a filter bypass circuit for bypassing said configurable low pass filter.
16. The input module of claim 15 , further comprising a high-speed enable feature, wherein said high speed enable feature comprises bypassing said configurable low pass filter to pass high speed signals while binning said pixels together.