Programmable logic devices comprising time multiplexed programmable interconnect
View Patent ↗A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval.
1. A time multiplexed programmable switch of a programmable logic device, the switch comprising:
a first node and a second node; and
a plurality of time multiplexed control signals, each signal coupled to a plurality of devices and having a non overlapping activation time interval; and
a plurality of paths to couple the first node to the second node, each path comprising:
a first device configured to an on state or an off state by a configurable element; and
a second device configured to an on state or an off state by said time multiplexed control signal, the second device positioned in series with the first device;
wherein, the first node is coupled to the second node by the path that comprises a first device that has an on state and during a time period when the second device has an on state.
2. The device of claim 1 , wherein the on state of the second device of a said path does not overlap with the on state of the second device in any other of said paths.
3. The device of claim 1 , wherein the first and second devices are integrated into a single device.
4. The device of claim 1 , wherein one or both of said first and second device comprises a pass-gate transistor.
5. The device of claim 1 , wherein the configurable element of the first device is one of a random access memory (RAM) element and a read only memory element (ROM).
6. The device of claim 1 , wherein the configurable element of the first device comprises one of a volatile and non-volatile memory element.
7. The device of claim 1 , comprising a configuration circuit.
8. The device of claim 1 , comprising one of: a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electro-magnetic cell, a carbon nano-tube, an optical element and a magnetic memory element.
9. A time multiplexed programmable switch of a programmable logic device, the switch comprising:
a plurality of nodes in a first set; and
a second node; and
a plurality of digital signals, each signal coupled to a plurality of devices and comprising a non overlapping activation time interval; and
a plurality of paths to couple each node in the first set to the second node, each of said paths
comprising:
a first device configured to an on state or an off state by a configurable element; and
a second device configured to an on state or an off state by said digital signal, the second device positioned in series with the first device;
wherein, each node in the first set is selectively coupled to the second node by a path that comprises an on state of the first device and a time period during which the second device has an on state.
10. The device of claim 9 , wherein no more than one of the first set nodes is coupled to the second node at any given time.
11. The device of claim 9 , wherein the said second device within one coupling path from each said first set nodes to the second node share a common digital signal.
12. The device of claim 9 , wherein a plurality of nodes in the first set is selectively coupled one node at a time to the second node by the digital signals.
13. The device of claim 9 , wherein for the plurality of paths from each node in the first set to the second node, only one of the paths has a first device configured to on state.
14. The device of claim 9 , wherein the first and second devices in series are integrated into a single device.
15. The device of claim 9 , wherein one or both of said first and second device comprises a pass-gate transistor.
16. The device of claim 9 , wherein a said configurable element of the first device is one of a random access memory (RAM) element and a read only memory element (ROM).
17. The device of claim 9 , wherein a said configurable element of the first device comprises one of a volatile and non-volatile memory element.
18. The device of claim 9 , comprising a configuration circuit.
19. The device of claim 9 , comprising one of: a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electro-magnetic cell, a carbon nano-tube, an optical element and a magnetic memory element.
20. A time multiplexed programmable switch of a semiconductor device comprising:
a first node;
a plurality of digital signals, each signal coupled to a plurality of devices and comprising a non overlapping activation time interval; and
a plurality of second nodes, each of the second nodes having a path to couple to the first node,
the path comprising:
a first configurable device configured to select or deselect the path; and
a second configurable device in series with the first configurable device configured to select or deselect the path by said digital signal;
wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval.