Sigma-delta modulator for PWM applications with minimum dynamical control and dithering
The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.
1. A sigma-delta Pulse-Width-Modulation (PWM) modulator comprising:
an input gain stage;
a first sigma-delta circuit to receive on a first input an amplified analog input signal of the input gain stage and on a second input a feedback signal;
a PWM output quantizer stage input with an output signal from the sigma-delta circuit;
a feedback path connected between the PWM output quantizer stage and the sigma-delta circuit to provide the feedback signal, and comprising a delay network; and
a second sigma-delta circuit, between an output of the first sigma-delta circuit and an input of the PWM output quantizer stage, and input with a sum of the output signal of the first sigma-delta circuit and a delayed signal corresponding to a difference between a signal at the input and at the output of the second sigma-delta circuit.
2. The sigma-delta PWM modulator of claim 1 , further comprising a generator to add to the analog input signal that is input to the first sigma-delta circuit a periodic ramp signal having a frequency based upon a PWM quantization frequency, and having an amplitude based upon a maximum amplitude of the analog input signal.
3. The sigma-delta PWM modulator of claim 2 wherein the frequency of the periodic ramp signal comprises at least one of a frequency equal to the PWM quantization frequency and a frequency varying within a range centered on the PWM quantization frequency.
4. The sigma-delta PWM modulator of claim 2 , wherein the generator comprises a counter, a reference value latch, an adder of a count value present at the output of the counter and of a reference value stored in the latch, and an output gain stage for the periodic ramp signal based upon a clock signal driving the counter and the reference value stored in the latch.
5. A sigma-delta Pulse-Width-Modulation (PWM) modulator comprising:
an input gain stage;
a first sigma-delta circuit to receive an input signal from the input gain stage and a feedback signal;
a PWM output quantizer stage to receive an output signal from the sigma-delta circuit;
a feedback path associated with the PWM output quantizer stage and the sigma-delta circuit to provide the feedback signal; and
a second sigma-delta circuit coupled between the first sigma-delta circuit and the PWM output quantizer stage, and to receive a sum of the output signal from the first sigma-delta circuit and a delayed signal corresponding to a difference between an input signal and an output signal of the second sigma-delta circuit.
6. The sigma-delta PWM modulator of claim 5 , further comprising a generator to add to the input signal that is input to the first sigma-delta circuit a periodic ramp signal having a frequency based upon a PWM quantization frequency, and having an amplitude based upon a maximum amplitude of the analog input signal.
7. The sigma-delta PWM modulator of claim 6 wherein the frequency of the periodic ramp signal comprises at least one of a frequency equal to the PWM quantization frequency and a frequency varying within a range centered on the PWM quantization frequency.
8. The sigma-delta PWM of claim 6 , wherein the generator comprises a counter, a reference value latch, an adder of a count value present at the output of the counter and of a reference value stored in the latch, and an output gain stage for the periodic ramp signal based upon a clock signal driving the counter and the reference value stored in the latch.
9. A method of sigma-delta Pulse-Width-Modulation (PWM) comprising:
providing an input signal and a feedback signal to a first sigma-delta circuit;
providing an output signal from the sigma-delta circuit to a PWM output quantizer stage;
providing the feedback signal via a feedback path associated with the PWM output quantizer stage and the sigma-delta circuit; and
coupling a second sigma-delta circuit between the first sigma-delta circuit and the PWM output quantizer stage, and inputting thereto, a sum of the output signal from the first sigma-delta circuit and a delayed signal corresponding to a difference between an input signal and an output signal of the second sigma-delta circuit.
10. The method of claim 9 , further comprising adding to the input signal that is input to the first sigma-delta circuit a periodic ramp signal having a frequency based upon a PWM quantization frequency, and having an amplitude based upon a maximum amplitude of the input signal.
11. The method of claim 10 wherein the frequency of the periodic ramp signal comprises at least one of a frequency equal to the PWM quantization frequency and a frequency varying within a range centered on the PWM quantization frequency.
12. The sigma-delta PWM of claim 10 , wherein the periodic ramp signal is provided by a generator comprising a counter, a reference value latch, an adder of a count value present at the output of the counter and of a reference value stored in the latch, and an output gain stage for the periodic ramp signal based upon a clock signal driving the counter and the reference value stored in the latch.