Iterative decoder using input data pipelining and time-interleaved processing

1. A decoder architecture comprising:

an input buffer configured to receive and store one or more codewords to be processed;

a decoder coupled to the input buffer, the decoder configured to receive a first codeword and a second codeword from the input buffer, and simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed for time durations corresponding to actual decoding times for the first and second codewords;

an output buffer configured to receive and store codewords output from the decoder, the output buffer to output each codeword stored in the output buffer at a fixed rate; and

wherein the input buffer is further configured to load a third codeword into the decoder responsive to the completed decoding of the first codeword or the second codeword.

2. The decoder architecture of claim 1 , wherein the first codeword is loaded into the decoder without waiting for the second codeword to be ready to be loaded into the decoder.

3. The decoder architecture of claim 1 , wherein the first codeword is loaded into the decoder simultaneously with the second codeword.

4. The decoder architecture of claim 1 , wherein the output buffer comprises a FIFO (First-In, First-Out) buffer to outputs each codeword in the same order in which each codeword is loaded into the decoder.

5. The decoder architecture of claim 1 , wherein the decoder includes logic to determine when a given codeword being processed by the decoder has become decoded and generate a strobe signal that loads a next codeword from the input buffer into the decoder.

6. The decoder architecture of claim 5 , further comprising a time limit counter configured to limit a maximum processing time of any given codeword, wherein once the time limit counter has reached a pre-determined maximum time limit, the time limit counter triggers a load of a next codeword from the input buffer into the decoder.

7. The decoder architecture of claim 1 , wherein:

the input buffer is a FIFO (First-In, First-Out) buffer; and

the decoder is an iterative decoder.

8. The decoder architecture of claim 7 , wherein the iterative decoder is one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Reed-Solomon decoder.

9. A method for processing codewords, the method comprising:

loading one or more codewords to be processed in an input buffer at a first rate;

loading a first codeword and a second codeword into a decoder one at a time at a second rate from the input buffer, the decoder to simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed for time durations corresponding to actual decoding times for the first and second codewords;

buffering the output from the decoder into an output FIFO buffer, and outputting each codeword from the output buffer at a fixed rate; and

loading a third codeword into the decoder responsive to the completed decoding of the first codeword or the second codeword.

10. The method of claim 9 , wherein processing a given codeword in the decoder only for a minimum amount of time for the codeword to become decoded includes generating a strobe signal that loads a next codeword from the input buffer into the decoder responsive to a determination that the given codeword being processed by the decoder has become error free.

11. The method of claim 10 , wherein:

the input buffer is a FIFO (First-In, First-Out) buffer; and

the decoder is an iterative decoder.

12. The method of claim 11 , wherein the iterative decoder is one of a low density parity check (LDPC) decoder, a Hamming decoder, or a Reed-Solomon decoder.

13. The method of claim 9 , wherein the first rate and the second rate are different.

14. The decoder architecture of claim 1 wherein the decoder comprises:

a plurality of equality constraint nodes;

a plurality of parity check nodes; and

an interleave path coupling the equality constraint nodes to the parity check nodes, wherein respective codewords iterate between the equality constraint nodes and the parity check nodes.