IP Library Granted Patent US 7,692,458
Granted Patent B1
US 7,692,458 · App. 12/249,915 · Granted Apr 6, 2010

Wide dynamic range charge pump

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Quick Facts
Patent No.
US 7,692,458
App. No.
12/249,915
Granted
Apr 6, 2010
Kind
B1
Abstract

A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.

Claims (59)

1. A wide dynamic range charge pump comprising:

a first, second, and third set of current sources, each set comprising:

a top source connected to a first reference voltage and a top signal input, and an output to supply current responsive to a top signal; and,

a bottom source connected to the top source output and a bottom signal input, and an output connected to a second reference voltage, different than the first reference voltage, to supply current in response to a bottom signal;

a first capacitor having an input connected to the first set top source output, and an output connected to the second reference voltage;

a first operational amplifier (op amp) having an input connected to the first set top source output, and an output connected to the second set top source output;

a first resistor having a first end connected to the first op amp output and a second end connected to the third set top source output;

a second capacitor having an input connected to the first resistor second end, and an output connected to the second reference voltage;

wherein the first set receives a phase detector/phase-frequency detector (PHD/PFD) first output as the top signal and a PHD/PFD second output as the bottom signal input, to supply a first current (Iap) from the top source output in response to the difference between the top and bottom signal inputs;

wherein the second set receives the PFD first output as the bottom signal and the PHD/PFD second output as the top signal input, to supply a second current (Ibp 2 ) from the top source output in response to the difference between the top and bottom signal inputs; and,

wherein the third set receives the PHD/PFD first output as the top signal and the PHD/PFD second output as the bottom signal input, to supply a third current (Ibp 1 ) from the top source output in response to the difference between the top and bottom signal inputs.

2. The charge pump of claim 1 wherein the first set supplies an average value of Iap; and,

wherein the second and third sets supply currents Ibp 2 and Ibp 1 , respectively, each having an average value greater than the first average value of Iap.

3. The charge pump of claim 2 wherein the average value sum of Ibp 1 and Ibp 2 is approximately zero.

4. The charge pump of claim 3 wherein the sum of the Ibp 1 and Ibp 2 instantaneous values at any particular time is approximately zero.

5. The charge pump of claim 2 wherein |Iap|<|Ibp 1 | and |Iap|<|Ibp 2 |.

6. The charge pump of claim 1 wherein the first op amp is a unity-gain op amp.

7. The charge pump of claim 1 further comprising:

a fourth, fifth, and sixth set of current sources, each set comprising:

a top source connected to the first reference voltage and a top signal input, and an output to supply current responsive to a top signal; and,

a bottom source connected to the top source output, and a bottom signal input, and an output connected to a second reference voltage, different than the first reference voltage, to supply current in response to a bottom signal;

a third capacitor having an input connected to the fourth set top source output, and an output connected to the second reference voltage;

a second op amp having an input connected to the fourth set top source output, and an output connected to the fifth set top source output;

a second resistor having a first end connected to the second op amp output and a second end connected to the sixth set top source output;

a fourth capacitor having an input connected to the second resistor second end, and an output connected to the second reference voltage;

wherein the fourth set receives a PHD/PFD first differential output as the top signal and a PHD/PFD second differential output as the bottom signal input, to supply a fourth current (Ian) from the top source output in response to the difference between the top and bottom signal inputs;

wherein the fifth set receives the PHD/PFD first differential output as the bottom signal and the PHD/PFD second differential output as the top signal input, to supply a fifth current (Ibn 2 ) from the top source output in response to the difference between the top and bottom signal inputs; and,

wherein the sixth set receives the PHD/PFD first differential output as the top signal and the PHD/PFD second differential output as the bottom signal input, to supply a sixth current (Ibn 1 ) from the top source output in response to the difference between the top and bottom signal inputs.

8. The charge pump of claim 7 wherein the fourth set supplies an average value of Ian; and,

wherein the fifth and sixth sets supply currents Ibn 2 and Ibn 1 , respectively, each having an average value greater than the first average value of Ian.

9. The charge pump of claim 8 wherein the average value sum of Ibn 1 and Ibn 2 is approximately zero.

10. The charge pump of claim 9 wherein the sum of the Ibn 1 and Ibn 2 instantaneous values at any particular time is approximately zero.

11. The charge pump of claim 8 wherein |Ian|<|Ibn 1 | and |Ian|<|Ibn 2 |.

12. The charge pump of claim 7 wherein the second op amp is a unity-gain op amp.

13. The charge pump of claim 7 wherein |Ian|=|Iap|, |Ibp 1 |=|Ibn 1 |, and |Ibp 2 |=|Ibn 2 |.

14. In a phase-locked loop (PLL) circuit, a method for controlling current in a wide dynamic range charge pump, the method comprising:

providing a PLL including a phase/frequency detector, a charge pump, and a voltage controlled oscillator (VCO), wherein the charge pump includes:

a first, second, and third set of current sources, each set including:

a top source connected to a first reference voltage and a top signal input, and an output to supply current responsive to a top signal; and,

a bottom source connected to the top source output and a bottom signal input, and an output connected to a second reference voltage, different than the first reference voltage, to supply current in response to a bottom signal;

a first capacitor having an input connected to the first set top source output, and an output connected to the second reference voltage;

a first operational amplifier (op amp) having an input connected to the first set top source output, and an output connected to the second set top source output and to a voltage controlled oscillator (VCO) input;

a first resistor having a first end connected to the first op amp output and a second end connected to the third set top source output;

a second capacitor having an input connected to the first resistor second end, and an output connected to the second reference voltage;

at the first set, receiving a phase detector/phase-frequency detector (PHD/PFD) first output as the top signal and a PHD/PFD second output as the bottom signal input;

supplying a first current (Iap) from the top source output responsive to the difference between the top and bottom signal inputs;

at the second set, receiving the PHD/PFD first output as the bottom signal and the PHD/PFD second output as the top signal input;

supplying a second current (Ibp 2 ) from the top source output responsive to the difference between the top and bottom signal inputs;

at the third set, receiving the PHD/PFD first output as the top signal and the PHD/PFD second output as the bottom signal input; and,

supplying a third current (Ibp 1 ) from the top source output response to the difference between the top and bottom signal inputs.

15. The method of claim 14 further comprising:

for a constant value of Ibp, decreasing PLL jitter transfer peaking in response to decreasing |Iap|; and,

for a constant value of Ibp, increasing PLL jitter transfer peaking in response to increasing |Iap|.

16. The method of claim 14 further comprising:

for a constant value of Iap, increasing the PLL bandwidth in response to increasing |Ibp|; and,

for a constant value of Iap, decreasing the PLL bandwidth in response to decreasing |Ibp|.

17. The method of claim 14 further comprising:

for a constant value of Iap, decreasing PLL jitter transfer peaking in response to increasing |Ibp|; and,

for a constant value of Iap, increasing PLL jitter transfer peaking in response to decreasing |Ibp|.

Assignments (3)
SECURITY INTEREST Recorded May 11, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 042444/0891 →
MERGER AND CHANGE OF NAME Recorded May 8, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 042423/0700 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2008
From: EKER, MEHMET
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 021670/0950 →