A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.
1. A data switch for an integrated circuit, comprising:
a link to receive input data packets from an independently modulated spread spectrum clock (SSC) enabled source, wherein the source has predetermined spread spectrum link clock frequency characteristics;
an output to transmit the data packets after passage through the switch;
a receive buffer, having a link side and a core side, to receive the SSC modulated input data packets from the link;
a transmit buffer to buffer the data packets for the output; and
a core clock that operates at a given frequency between predetermined error limits determined by oscillation accuracy alone, wherein the core clock is not SSC-enabled, wherein the frequency is set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.
2. The switch of claim 1 , wherein the receive buffer detects packet boundaries and delays initiating a core-side read operation for a delay period, wherein the delay period causes the receive buffer to delay initiating the core-side read operation until a sufficient portion of a data packet has been written to the receive buffer so as to ensure that the end of the data packet will have been received in the receive buffer by the time the core is ready to read the end of the data packet.
3. The switch of claim 2 , wherein the delay period is a predetermined, fixed value.
4. The switch of claim 2 , wherein the delay period is a value giving minimum latency.
5. The switch of claim 2 , further comprising a controller to dynamically adjust the delay period in accordance with a detected packet size and an instantaneous frequency difference between the source clock and the core clock.
6. The switch of claim 5 , wherein the controller adjusts the delay period minimize latency.
7. The switch of claim 2 , further comprising a timer to initiate the core-side read operation at a predetermined time after a packet has been received.
8. The switch of claim 1 , further comprising a receive link layer situated on the link side of the receive buffer.
9. The switch of claim 8 , wherein the link comprises a single lane link and wherein the receive link layer detects packet boundaries.
10. The switch of claim 8 , wherein the link comprises a multi-lane link and wherein the link layer aligns bytes of a data packet distributed across the lanes and detects packet boundaries.
11. The switch of claim 8 , wherein the link layer has a link side and a core side, and wherein a boundary between a link clock domain and a core clock domain is located between the core side of the link layer and the core side of the receive buffer.
12. The switch of claim 1 , wherein a boundary between a link clock domain and a core clock domain is located between the link side of the receive buffer and the core side of the receive buffer.
13. A method of data switching for an integrated circuit comprising:
receiving spread spectrum clock (SSC) modulated input data packets with a receive buffer, having a link side and a core side, of a link for receiving input data packets from an independently modulated SSC enabled source, having predetermined spread spectrum link clock frequency characteristics, of a switch;
determining a clock frequency between predetermined error limits determined by oscillation accuracy alone at a level at least as high as a highest link clock frequency such that the receive buffer cannot be filled faster from its link side that it can be emptied from its core side;
operating a core clock that is not SSC-enabled at the determined clock frequency; and
transmitting the data packets after passage through the switch.
14. The method of claim 13 , further comprising detecting, with the receive buffer, packet boundaries;
determining a delay that will allow a sufficient portion of a data packet to be written to the receive buffer so as to ensure that the end of the data packet will have been received in the receive buffer by the time the core is ready to read to end of the data packet; and
delaying initiation of a core-side read operation in accordance with the delay.
15. The method of claim 14 , wherein determining a delay comprises setting the delay to a predetermined, fixed value.
16. The method of claim 14 , wherein determining a delay comprises setting the delay to a value giving minimum latency.
17. The method of claim 14 , wherein determining a delay comprises dynamically adjusting the delay with a controller in accordance with a detected packet size and an instantaneous frequency difference between the source clock and the core clock.
18. The method of claim 17 , further comprising adjusting the delay with the controller to minimize latency.
19. The method of claim 14 , further comprising:
starting a timer when a packet is received; and
triggering the core-side read operation when the timer reaches a predetermined time.
20. The method of claim 13 , further comprising situating a receive link layer on the link side of the receive buffer.
21. The method of claim 20 , wherein receiving comprises receiving SSC modulated input data packets with a single lane link, further comprising:
detecting packet boundaries with the receive link layer.
22. The method of claim 20 , wherein receiving comprises receiving SSC modulated input data packets with a multi-lane link, further comprising:
aligning bytes of a data packet distributed across lanes of the multi-lane link with the receive link layer; and
detecting packet boundaries with the receive link layer.
23. The method of claim 20 , wherein situating a receive link layer comprises situating the receive link layer to have a link side and a core side, further comprising:
determining a location of a boundary between a link clock domain and a core clock domain as being between the core side of the link layer and the core side of the receive buffer.
24. The method of claim 13 , further comprising determining a location of a boundary between a link clock domain and a core clock domain as being between the link side of the receive buffer and the core side of the receive buffer.