Semiconductor device
View Patent ↗There is provided a semiconductor storage device having a memory cell including a transfer transistor, a load transistor and a drive transistor, which includes a first transfer transistor to become conductive by a potential applied to a first word line placed in parallel with a pair of bit lines, a second transfer transistor to become conductive by a potential applied to a second word line placed orthogonal to the pair of bit lines, and a control circuit to output a control signal for controlling the potentials of the first word line and the second word line in such a way that the first transfer transistor becomes conductive earlier than the second transfer transistor when setting both of the first transfer transistor and the second transfer transistor to a conductive state.
1. A semiconductor storage device having a memory cell including a transfer transistor, a load transistor and a drive transistor, comprising:
a first transfer transistor to become conductive by a potential applied to a first word line placed in parallel with a pair of bit lines;
a second transfer transistor to become conductive by a potential applied to a second word line placed orthogonal to the pair of bit lines; and
a control circuit to output a control signal for controlling the potentials of the first word line and the second word line in such a way that the first transfer transistor becomes conductive earlier than the second transfer transistor when setting both of the first transfer transistor and the second transfer transistor to a conductive state.
2. The semiconductor storage device according to claim 1 , wherein
the first transfer transistor is connected to a connection point between the load transistor and the drive transistor, and
the second transfer transistor is connected between the first transfer transistor and a bit line.
3. The semiconductor storage device according to claim 1 , wherein
the first word line is placed between the pair of bit lines with respect to an extending direction of the second word line.
4. The semiconductor storage device according to claim 1 , wherein
the first word line is placed in the same layer as the pair of bit lines.
5. The semiconductor storage device according to claim 1 , wherein
the first transfer transistor becomes conductive earlier than the second transfer transistor at least by a period necessary for a potential level of the first word line to rise to High level.
6. The semiconductor storage device according to claim 1 , wherein
a plurality of memory cells each including the first transfer transistor and the second transfer transistor are connected to one pair of bit lines.