Method for manufacturing semicondcutor device
View Patent ↗A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used. This results in improved manufacturing efficiency and reduced manufacturing costs of a SONOS semiconductor device.
1. A method for manufacturing a SONOS semiconductor device comprising:
simultaneously forming a device isolation layer in a semiconductor substrate to define a memory region and a logic region, and also forming device isolation layers to define the logic region into an ultra-high voltage region, a high voltage region and a low voltage region; and then
forming an ONO layer in the logic region and the memory region by sequentially forming a first oxide layer, a nitride layer and a second oxide layer over the entire surface of the semiconductor substrate; and then
forming a first photoresist pattern in the memory region and the high voltage region; and then
forming an ONO layer pattern in the memory region and the high voltage region by implementing a first etching process using the first photoresist pattern as a mask; and then
removing the first photoresist pattern; and then
depositing a first silicon oxide material over the entire surface of the semiconductor substrate; and then
forming a second photoresist pattern in the memory region and the ultra-high voltage region; and then
simultaneously removing the second oxide layer of the ONO layer pattern in the high voltage region while forming a first gate oxide layer pattern composed of the first silicon oxide material in the memory region and the ultra-high voltage region by implementing a second etching process using the second photoresist pattern as a mask; and then
removing the nitride layer of the ONO layer pattern in the high voltage region by implementing a third etching process on the semiconductor substrate; and then
removing the second photoresist pattern; and then
forming a second gate oxide layer pattern over the entire surface of the semiconductor substrate semiconductor substrate including the low voltage region.
2. The method of claim 1 , wherein the device isolation layer is formed via local oxidation of silicon (LOCOS).
3. The method of claim 1 , wherein the device isolation layer is formed via shallow trench isolation (STI).
4. The method of claim 1 , wherein the second etching process is a wet etching.
5. The method of claim 4 , wherein the wet etching uses phosphoric acid (P 2 O 5 ) as an etching solution.
6. The method of claim 1 , wherein the third etching process is a wet etching process.
7. The method of claim 6 , wherein the wet etching uses hydrofluoric (HF) acid as an etching solution.
8. The method of claim 1 , wherein forming the ONO layer pattern comprises removing portions of the ONO layer in the low voltage and the ultra-high voltage region while leaving an ONO layer patterns in the memory region and the high voltage region.
9. The method according to claim 1 , wherein simultaneously removing the second oxide layer while forming the first gate oxide layer pattern comprises:
removing a portion of the first silicon oxide in the low voltage region and the high voltage region while leaving a portion of the first silicon oxide layer in the memory region and the ultra-high voltage region; and then
removing the second oxide layer of the ONO layer pattern in the high voltage region.
10. The method of claim 1 , wherein the nitride layer of the ONO pattern in the high voltage region is removed by an etching process using hydrofluoric (HF) acid as an etching solution.
11. A method for manufacturing a SONOS semiconductor device comprising:
simultaneously forming a first device isolation layer in a semiconductor substrate to define a memory region and a logic region, and also forming second device isolation layers to define the logic region into a first logic region, a second logic region and a third logic region; and then
forming an ONO layer by sequentially forming a first oxide layer, a nitride layer and a second oxide layer in the memory region, the first logic region, the second logic region and the third logic region; and then
forming a first photoresist pattern in the memory region and the second logic region; and then
forming an ONO layer pattern in the memory region and the second logic region by performing a first etching process using the first photoresist pattern as a mask and then removing the first photoresist pattern; and then
depositing a first silicon oxide in the memory region, the first logic region, the second logic region and the third logic region; and then
forming a second photoresist pattern in the memory region and the first logic region; and then
simultaneously removing the second oxide layer of the ONO layer pattern in the second logic region and forming a first gate oxide layer pattern in the memory region and the first logic region by performing a second etching process using the second photoresist pattern as a mask; and then
removing the nitride layer of the ONO layer pattern in the second logic region by performing a third etching process; and then
removing the second photoresist pattern; and then
forming a second gate oxide layer pattern in the memory region, the first logic region, the second logic region and the third logic region.
12. The method of claim 11 , wherein the first logic region comprises an ultra-high voltage region, the second logic region comprises a high voltage region and the third logic region comprises a low voltage region.
13. The method of claim 12 , wherein forming the ONO layer pattern comprises exposing the semiconductor substrate in the low voltage region and the ultra-high voltage region.
14. The method of claim 12 , wherein the second etching process is performing using the nitride layer in the high voltage region as a hard mask.
15. The method of claim 12 , wherein forming the second gate oxide layer pattern comprises forming the second gate oxide layer pattern on and contacting the semiconductor substrate in the low voltage region, on and contacting the first oxide layer in the high voltage region, on and contacting the first gate oxide layer pattern in the ultra-high voltage region and on and contacting the first gate oxide layer pattern in the memory region.
16. The method of claim 12 , wherein the nitride layer in the ONO pattern of the high voltage region is removed by an etching process using hydrofluoric (HF) acid as an etching solution.
17. The method of claim 11 , wherein the first gate oxide layer and the second gate oxide layer are composed of silicon oxide.
18. The method of claim 11 , wherein the first and second device isolation layers comprise shallow trench isolation layers.
19. The method of claim 11 , wherein the second etching process comprises a wet etching using phosphoric acid (P 2 O 5 ) as an etching solution.
20. The method of claim 11 , wherein the third etching process comprises a wet etching process using hydrofluoric (HF) acid as an etching solution.