Semiconductor device having vertical and horizontal type gates and method for fabricating the same
View Patent ↗A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device.
1. A semiconductor device comprising:
a high-density first conduction-type substrate;
a low-density first conduction-type epitaxial layer formed over the high-density first conduction-type substrate;
a plurality of first low-density second conduction-type base regions and second low-density second conduction-type base regions formed spaced apart in the low-density first conduction-type epitaxial layer;
a high-density first conduction-type source region formed in the first and second low-density second conduction-type base regions;
a high-density first conduction-type drain region formed in the epitaxial layer disposed outside of the first and second low-density second conduction-type base regions;
a high-density second type dopant region formed in the first low-density second conduction-type base regions;
a first gate electrode formed extending through the high-density first conduction-type source region of the second low-density second conduction-type base regions, the second low-density second conduction-type base regions and the first low-density second conduction-type base regions;
forming a field oxide layer over the low-density first conduction-type epitaxial layer between the first and second base region and a respective high-density first conduction-type drain region; and
a second gate electrode formed over the first and second low-density second conduction-type base regions between the high-density first conduction-type source region and the high-density first conduction-type drain region.
2. The semiconductor device of claim 1 , wherein the first gate electrode is formed in the first low-density second conduction-type base regions between the high-density second conduction-type dopant region and the high-density first conduction-type source region.
3. The semiconductor device of claim 1 , wherein the trenches are formed in the center of a respective first and second low-density second conduction-type base region.
4. The semiconductor device of claim 1 , wherein the high-density first conduction-type drain region is electrically connected to the high-density first conduction-type substrate.
5. The semiconductor device of claim 1 , further comprising:
a source line electrically connecting the respective high-density first conduction-type source regions; and
a drain line electrically connecting the respective high-density first conduction-type drain regions.
6. The semiconductor device of claim 1 , wherein the first gate electrodes and the second gate electrodes are interconnected at one terminal of the semiconductor device.
7. The semiconductor device of claim 1 , wherein the first gate electrode comprises a vertical-type gate electrode.
8. The semiconductor device of claim 1 , further comprising an interlayer dielectric layer formed over an uppermost surface and lateral sidewalls of the first gate electrode and the second gate electrode.
9. The semiconductor device of claim 3 , wherein the high-density first conduction-type source region is formed in the first low-density second conduction-type base regions disposed laterally at one side of the first gate electrode.
10. The semiconductor device of claim 9 , wherein the high-density second conduction-type dopant region is formed in the first low-density second conduction-type base regions disposed laterally at the other side of the first gate electrode.
11. The semiconductor device of claim 10 , wherein high-density second conduction-type dopant region comprises a protection diode.
12. The semiconductor device of claim 8 , wherein the second gate electrodes comprise horizontal-type gate electrodes.
13. The semiconductor device of claim 12 , further comprising a source line layer electrically connected to a respective high-density first conduction-type source region and a drain line layer electrically connected to a respective high-density first conduction-type drain region over the interlayer dielectric layer.
14. A method for fabricating a semiconductor device comprising:
forming a low-density first conduction-type epitaxial layer over a high-density first conduction-type substrate; and then
forming a plurality of first low-density second conduction-type base regions and second low-density second conduction-type base regions spaced apart in the low-density first conduction-type epitaxial layer; and then
simultaneously forming a high-density first conduction-type source region in the first and second low-density second conduction-type base regions and a high-density first conduction-type drain region in the epitaxial layer disposed outside of the first and second low-density second conduction-type base regions; and then
forming high-density second type dopant regions in the first low-density second conduction-type base regions; and then
forming a trench to penetrate the high-density first conduction-type source region of the second low-density second conduction-type base regions, the second low-density second conduction-type base regions and the first low-density second conduction-type base regions; and then
forming a first gate electrode in a respective trench; and then
forming a field oxide layer over the low-density first conduction-type epitaxial layer between the first and second low-density second conduction-type base regions and a respective high-density first conduction-type drain region; and then
forming a second gate electrode over the first and second low-density second conduction-type base regions between the high-density first conduction-type source region and the high-density first conduction-type drain region.
15. The method of claim 14 , wherein the first gate electrode is formed in the first low-density second conduction-type base regions between the high-density second conduction-type dopant region and the high-density first conduction-type source region.
16. The method of claim 14 , wherein the high-density first conduction-type drain region is electrically connected to the high-density first conduction-type substrate.