Nonvolatile memory device and method for fabricating the same
View Patent ↗A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.
1. A nonvolatile memory device comprising:
a plurality of floating gates formed on a tunnel oxide layer that is formed on a semiconductor substrate;
a source region and a drain region formed alternately in the substrate between neighboring floating gates; and the drain region being overlapped with the neighboring floating gates;
a word line formed over the floating gate and being across the substrate in one direction;
wherein said word line includes first and second portions between the neighboring floating gates on the tunnel oxide and over the source region and the drain region, respectively, and the first portion of the word line has a width greater than a width of the second portion; and
a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.
2. The nonvolatile memory device of claim 1 , wherein the word line comes across over the plurality of floating gates.
3. The nonvolatile memory device of claim 2 , wherein the plurality of floating gates are disposed both in row and column direction of the substrate, a plurality of the word lines come across the semiconductor substrate, and the source and drain regions and the field oxide layer are formed across the word lines.
4. The nonvolatile memory device of claim 1 further comprising a gate oxide layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region.
5. The nonvolatile memory device of claim 1 , wherein the source and drain regions are formed in the substrate while intersecting the word line.
6. The nonvolatile memory device of claim 1 further comprising an inter-gate insulating layer interposed between top surface of the floating gate and the word line.
7. A nonvolatile memory device comprising:
a plurality of the floating gates formed on a tunnel oxide layer that is formed on a semiconductor substrate;
a source region and a drain region formed alternatively in the substrate between neighboring floating gates, and the drain region being overlapped with the neighboring floating gates;
a gate oxide layer formed on a portion of an active region between the source region and the respective floating gate and on a sidewall of the respective floating gate directing toward the source region, as well as on a sidewall of the respective floating gate directing toward the drain region;
a word line formed over the floating gates and being across the substrate in one direction; and
a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line,
wherein said word line includes first and second portions between the neighboring floating gates on the tunnel oxide and over the source region and the drain region, respectively, and
the first portion of the word line has a width greater that a width of the second portion.
8. The nonvolatile memory device of claim 7 , wherein a thickness of the field oxide layer, above the source and drain regions, is greater than a thickness of the gate oxide layer.