Granted Patent B2

US 7,796,404 · App. 12/257,363 · Granted Sep 14, 2010

Abstract

Claims (56)

1. A synchronous field effect transistor (FET) power controller, comprising:

a first rectifying FET;

a first driver coupled to said first rectifying FET that is configured to both:

(a) activate said first rectifying FET if said first driver senses an activation body diode conduction current of said first rectifying FET, and

(b) deactivate said first rectifying FET if said first driver receives a first deactivation signal; and

a first primary FET that is deactivated by a delay of said first deactivation signal; and wherein said delay lessens a duration of a conduction time of a deactivation body diode conduction current of said first rectifying FET;

wherein a positive node of an output port is coupled to a center tap of a secondary winding of a transformer coupled to said first rectifying FET.

2. The power controller of claim 1 wherein said delay of said first deactivation signal minimizes said duration of said conduction time of said deactivation body diode conduction current of said first rectifying FET.

3. The power controller of claim 1 wherein said delay of said first deactivation signal is programmable.

4. The power controller of claim 1 wherein said driver is configured to not activate said rectifying FET if said driver senses a body conduction current that is a deactivation body diode conduction current.

5. The power controller of claim 1 wherein said activation body diode conduction current of said first rectifying FET begins before both said first primary FET and before said first rectifying FET is activated.

6. The power controller of claim 1 further comprising:

a second rectifying FET;

a second driver coupled to said second rectifying FET that is configured to both:

(a) activate said second rectifying FET if said second driver senses a second activation body diode conduction current of said second rectifying FET, and

(b) deactivate said second rectifying FET if said second driver receives a second deactivation signal; and

a second primary FET that is deactivated by a second delay of said second deactivation signal wherein said second delay lessens a duration of a conduction time of a second deactivation body diode conduction current of said second rectifying FET.

7. The power controller of claim 6 wherein said first primary FET and said second primary FET not active simultaneously.

8. The power controller of claim 6 further comprising a voltage controlled oscillator coupled to said first and second rectifying FETs to generate said deactivation signals.

9. The power controller of claim 1 further comprising said first rectifying FET having a channel conduction path after said first rectifying FET is activated by said first driver.

10. The power controller of claim 1 wherein said FET comprises a metal oxide semiconductor field effect transistor (“MOSFET”).

11. The power controller of claim 1 wherein said first driver further comprises a body diode conduction sensor that detects a body diode conduction current by measurement of a body diode conduction voltage of said first rectifying FET.

12. The power controller of claim 1 wherein a resonance frequency occurs due to an interaction between an inductor, a transformer, and a capacitor on a primary side of said power controller, and a firing frequency of said first primary FET is less than said resonance frequency.

13. A method for operating a power controller, comprising:

activating a rectifying FET upon a detection of an activation body diode conduction current occurring in said rectifying FET;

generating an activation signal for a corresponding primary FET;

deactivating said corresponding rectifying FET upon a reception of a deactivation signal; and

deactivating said corresponding primary FET after delaying said deactivation signal wherein said delay lessens a conduction time of a deactivation body current of said corresponding rectifying FET;

wherein a positive node of an output port is coupled to a center tap of a secondary winding of a transformer coupled to said first rectifying FET.

14. The method of claim 13 wherein said delay of said deactivation signal minimizes said duration of said conduction time of said deactivation body diode conduction current of said rectifying FET.

15. The method of claim 13 wherein said delay is programmable.

16. The method of claim 13 further comprising:

activating a second rectifying FET upon a detection of an activation body diode conduction current occurring in said second rectifying FET;

generating an activation signal for a corresponding second primary FET;

deactivating said corresponding second rectifying FET upon a reception of a second deactivation signal; and

deactivating said corresponding second primary FET after delaying said second deactivation signal wherein said second delay lessens a conduction time of a deactivation body current of said second corresponding rectifying FET.

17. The method of claim 16 wherein said first primary FET and said second primary FET are not in an active state simultaneously.

18. The method of claim 16 wherein a deactivation body diode conduction current of said corresponding rectifying FET is halted by an activation of a second primary FET wherein said activation is determined by a second delay.

19. The method of claim 13 wherein said delay is proportional to an allotted time of a deactivation body diode current conduction of said corresponding rectifying FET after said rectifying FET is deactivated but before said first primary FET is deactivated.

20. The method of claim 13 further comprising determining a delay time of said delayed deactivation signal through an employment of operational tolerances of conduction parameters of at least said primary FET and at least said corresponding rectifying FET.

21. The method of claim 13 wherein said body diode conduction current occurs in said rectifying FET in response to a deactivation of a primary-non corresponding FET.

22. A power converter, comprising:

a plurality of primary field effect transistors (FETs);

a first primary inductor and a primary capacitor coupled to said plurality of primary FETs;

a transformer coupled to said primary capacitor;

a plurality of rectifying FETs coupled to said transformer;

a first and second driver, each of said first and second drivers coupled to a rectifying FET of said plurality of rectifying FETs wherein each driver is configured to:

(a) activate its coupled rectifying FET if a driver senses an activation body diode conduction current of its coupled rectifying FET, and

(b) deactivate its coupled rectifying FET if said driver receives a deactivation signal; and

wherein said primary FETs are each deactivated by a delay of a corresponding deactivation signal;

wherein said delays each lessen a duration of a conduction time of a deactivation body diode conduction current of said first and second rectifying FETs; and

wherein a positive node of an output port is coupled to a center tap of a secondary winding of a transformer coupled to said first rectifying FET.

23. The power converter of claim 22 wherein said first driver does not activate its coupled rectifying FET if said first driver senses a body diode conduction current in its coupled rectifying FET that is a deactivation body diode conduction current.

24. The power converter of claim 22 wherein said activation body diode conduction current of a first rectifying FET of said plurality of rectifying FETs begins after a first primary FET is activated of said primary FETs but before said first rectifying FET is activated.

25. The power converter of claim 22 wherein said first and second drivers each comprise a body diode conduction sensor that detects a body diode conduction current by measurement of a body diode conduction voltage.

26. The power converter of claim 22 wherein a resonance occurs due to an interaction between said first primary inductor, said transformer, and said primary capacitor, and a firing frequency of said first primary FET is less than said resonance frequency.

Assignments (9)