Test system, electronic device, and test apparatus
View Patent ↗Provided is a test system that tests a device under test, including a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal.
1. A test system that tests a device under test, comprising:
a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test;
a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and
a test apparatus that supplies the device control section with the external signal,
wherein the test apparatus includes:
a test circuit that tests the operation circuit; and
a synchronization control section that causes the test circuit and the internal test circuits to operate in synchronization,
the test system tests a plurality of the devices under test formed in a wafer under test,
the test apparatus further includes a test substrate that is arranged facing the wafer under test and on which is formed a plurality of circuit blocks corresponding to the plurality of devices under test, and
each circuit block includes the test circuit and the synchronization control section, and tests a corresponding device under test.
2. The test system according to claim 1 , wherein
the test apparatus further includes a tester-side control section that supplies the device control section with the external signal,
the test circuit operates according to a preset test cycle, and
the synchronization control section synchronizes the external signal generated by the tester-side control section with the test cycle.
3. The test system according to claim 2 , wherein
the tester-side control section generates an intra-tester control signal having a bit configuration that is substantially the same as a bit configuration of the intra-device control signal, to further control the test circuit.
4. The test system according to claim 3 , wherein
the tester-side control section generates the external signal that causes the internal test circuits to test the operation circuit, after the test circuit sets the operation circuit to a prescribed state.
5. The test system according to claim 4 , wherein
the device under test further includes:
an operation pin that performs input and output of a signal between the operation circuit and the outside of the device under test; and
a test pin that performs input and output of a signal between the device control section and the outside of the device under test,
the tester-side control section performs input and output of a signal to and from the device control section via the test pin, and
the test circuit performs input and output of a signal to and from the operation circuit via the operation pin.
6. The test system according to claim 5 , wherein
at least one of the internal test circuits includes an analog circuit that performs input and output of an analog signal,
the device under test further includes a calibration pin that is connected to the internal test circuit including the analog circuit, and
the test apparatus supplies the internal test circuit with a calibration signal via the calibration pin.
7. The test system according to claim 1 , wherein
the test apparatus further includes a BOST circuit that is formed on the test substrate and that tests the operation circuit via the test pins provided on the devices under test.