Integrated infrared and color CMOS imager sensor
An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels.
1. An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array comprising:
a lightly doped p doped silicon (Si) substrate;
a plurality of pixel cells, each pixel cell including:
at least one visible light detection pixels, each pixel including a moderately p doped bowl with a bottom p doped layer and p doped sidewalls, an n doped layer enclosed by the p doped bowl, a moderately p doped surface region overlying the n doped layer, and a transfer transistor with a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region;
an IR pixel including moderately p doped sidewalls, an n doped layer enclosed by the p doped sidewalls, a lightly p doped layer of p doped substrate underlying the n doped layer, a moderately p doped surface region overlying the n doped layer, and a transfer transistor with a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to the floating diffusion region; and,
an optical wavelength filter overlying the visible light and IR pixels.
2. The array of claim 1 wherein the bottom p doped layer of each visible light pixel is formed at a first depth, and wherein the n doped layers of each visible light pixel and the IR pixel are formed at a second depth.
3. The array of claim 1 wherein the pixel cell includes at least three visible light pixels include a first pixel, and second pixel, and a third pixel; and,
wherein the optical wavelength filter includes a first filter section transmitting a first wavelength of light in the visible spectrum and IR wavelengths, overlying the first pixel, a second filter section transmitting a second wavelength of light in the visible spectrum and the IR wavelengths, overlying the second pixel, a third filter section transmitting a third wavelength of light in the visible spectrum and the IR wavelengths, overlying the third pixel, and a fourth filter section transmitting IR wavelengths overlying the IR pixel.
4. The array of claim 3 wherein each visible light pixel includes a lightly p doped layer of the p doped substrate interposed between a top surface of the bottom p doped layer and a bottom surface of the n doped layer.
5. The array of claim 1 wherein the p doped Si substrate is an epitaxial layer having a thickness of at least 10 microns; and,
the array further comprising:
a lightly n doped substrate underlying the p doped Si epitaxial layer.
6. The array of claim 1 wherein at least one visible light detecting pixel and the IR pixel share a four transistor active pixel sensor (APS) with a common select transistor, a common reset transistor, a common follower transistor, and a common floating diffusion region.