Semiconductor memory, memory system, and memory access control method

1. A semiconductor memory comprising:

a memory core that includes a plurality of memory cells;

a refresh generation unit that generates a refresh request for refreshing the memory cell;

a core control unit that performs an access operation in response to an access request;

a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and deactivates the latency extension signal in response to deactivation of the chip enable signal;

a latency output buffer that outputs the latency extension signal; and

a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.

2. The semiconductor memory according to claim 1 , wherein the data control unit increases the latency in comparison with a latency during the deactivation of the latency extension signal.

3. The semiconductor memory according to claim 1 , wherein the core control unit performs the access operation in response to a first access request supplied along with the activation of the chip enable signal and a subsequent access request supplied during the activation of the chip enable signal, and further includes a latency control unit that outputs an extension reset signal when the subsequent access request is not supplied for a certain period.

4. The semiconductor memory according to claim 1 , wherein the latency includes at least one of a read latency in which read data is transferred to the data terminal based on a read request and a write latency in which write data is transferred to the data terminal based on a write request.

5. The semiconductor memory according to claim 3 , further comprising:

a mode register which sets a burst length indicating a number of times data inputted or outputted in response to the access request,

wherein the certain period is obtained by adding a clock cycle indicated by the burst length to a certain number of clock cycles.

6. The semiconductor memory according to claim 1 , wherein the latency output buffer outputs as the latency extension signal a pulse signal synchronized with the activation of the latency extension signal.

7. The semiconductor memory according to claim 1 , wherein the data control unit includes:

a burst counter that counts, in response to the access request, and outputs a burst clock signal upon a counter value reaching an expected value,

wherein the expected value is increased upon the activation of the latency extension signal.

8. The semiconductor memory according to claim 7 , further comprising:

a data register that transfers at least one of read data and write data in synchronization with the burst clock signal.

9. The semiconductor memory according to claim 1 , wherein

the core control unit performs the access operation in response to a first access request supplied along with the activation of the chip enable signal and a subsequent access request supplied during the activation of the chip enable signal, and

the data control unit sets a difference between a latency corresponding to the first access request and a latency corresponding to the subsequent access request during the activation of the latency extension signal equal to a difference between a latency corresponding to the first access request and a latency corresponding to the subsequent access request during the deactivation of the latency extension signal.

10. The semiconductor memory according to claim 8 , wherein the latency includes at least one of a read latency in which the read data is transferred to the data terminal based on a read request and a write latency in which the write data is transferred to the data terminal based on a write request.

11. The semiconductor memory according to claim 1 , further comprising:

a wait control unit that outputs a wait signal, which is activated in response to the access request and is deactivated before data corresponding to the access request is output.

12. The semiconductor memory according to claim 1 , wherein the core control circuit performs the access operation after a refresh operation upon the conflict between the activation of the chip enable signal and the refresh request.

13. A memory system comprising:

a semiconductor memory; and

a memory controller that supplies the semiconductor memory with an access request for accessing the semiconductor memory,

wherein the semiconductor memory includes:

a memory core that includes a plurality of memory cells;

a refresh generation unit that generates a refresh request for refreshing the memory cell;

a core control unit that performs an access operation in response to the access request;

a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and deactivates the latency extension signal in response to deactivation of the chip enable signal;

a latency output buffer that outputs the latency extension signal to an outside; and

a data control unit that changes a latency between the access request and transfer of data to the data terminal during the activation of the latency extension signal.

14. The memory system according to claim 13 , wherein the memory controller includes:

a system latency control unit that changes a system latency between output of the access request and the transfer of the data to the data terminal of the memory controller based on the latency extension signal output from the semiconductor memory.

15. The memory system according to claim 14 , wherein the system latency control unit increases the system latency in comparison with a system latency during the deactivation of the latency extension signal.

16. The memory system according to claim 13 , wherein the latency includes at least one of a read latency in which read data is transferred to the data terminal based on a read request and a write latency in which write data is transferred to the data terminal based on a write request.

17. The memory system according to claim 14 , wherein the core control unit performs the access operation in response to a first access request supplied along with the activation of the chip enable signal and a subsequent access request supplied during the activation of the chip enable signal, and

wherein the system latency control unit restores the changed system latency when the subsequent access request is not supplied for a certain period.

18. A memory access control method comprising:

performing an access operation on a plurality of memory cells in response to a first access request supplied along with activation of a chip enable signal and a subsequent access request supplied during the activation of the chip enable signal;

refreshing the plurality of memory cells in response to a refresh request;

activating a latency extension signal upon a conflict between the activation of the chip enable signal and the refresh request and deactivating the latency extension signal in response to deactivation of the chip enable signal;

outputting the latency extension signal; and

increasing a latency between the access request and a transfer of data to a data terminal during the activation of the latency extension signal.

19. The memory access control method according to claim 18 , further comprising:

deactivating the latency extension signal when the subsequent access request is not supplied for a certain period.

20. The memory access control method according to claim 18 , wherein the latency includes at least one of a read latency in which read data is transferred to the data terminal based on a read request and a write latency in which write data is transferred to the data terminal based on a write request.