Fast simulation method for integrated circuits with power management circuitry
In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.
1. A fast simulation method comprising:
accessing a netlist of a circuit;
identifying an output node of a power supply module of the circuit as a power node;
designating the power node an ideal power node;
partitioning the circuit into blocks, wherein the power supply module is designated a fan-in block and any blocks connected to the power node are designated fan-out blocks;
performing DC initialization for the circuit; and
for each time step:
determining any inter-relationship of the fan-out blocks, the determining any inter-relationship including identifying simulation intervals for each fan-out block;
calculating a sensitivity model for each fan-out block, the sensitivity model including conductance, capacitance, and current loadings;
asynchronously adding results of the sensitivity model for each fan-out block to a total loadings of the power node, the total loadings including delta values calculated based on results of a previous simulation interval and added to the total loadings;
loading the total loadings into a Jacobian matrix computed for the fan-in block; and
outputting a simulation waveform point.
2. The method of claim 1 , wherein asynchronously adding results includes tracking the total loadings using a global data structure.
3. The method of claim 2 , wherein tracking the total loading includes ignoring any inactive fan-out block.
4. The method of claim 1 , wherein a first simulation has delta values of zero for the total loadings.
5. The method of claim 1 , wherein circuits within each fan-out block are synchronously simulated.
6. The method of claim 1 , further including partitioning at least one fan-out block, designating an other ideal node in that fan-out block, and asynchronously simulating circuits fed by the other ideal node.
7. A non-transitory, computer-readable medium storing computer instructions that, when executed on a computer, generate signals that perform steps to simulate an integrated circuit, the steps comprising:
accessing a netlist of a circuit;
identifying an output node of a power supply module of the circuit as a power node;
designating the power node an ideal power node;
partitioning the circuit into blocks, wherein the power supply module is designated a fan-in block and any blocks connected to the power node are designated fan-out blocks;
performing DC initialization for the circuit; and
for each time step:
determining any inter-relationship of the fan-out blocks, the determining any inter-relationship including identifying simulation intervals for each fan-out block;
calculating a sensitivity model for each fan-out block, the sensitivity model including conductance, capacitance, and current loadings;
asynchronously adding results of the sensitivity model for each fan-out block to a total loadings of the power node, the total loadings including delta values calculated based on results of a previous simulation interval and added to the total loadings;
loading the total loadings into a Jacobian matrix computed for the fan-in block; and
outputting a simulation waveform point.
8. The computer-readable medium of claim 7 , wherein asynchronously adding results includes tracking the total loadings using a global data structure.
9. The computer-readable medium of claim 8 , wherein tracking the total loading includes ignoring any fan-out block.
10. The computer-readable medium of claim 7 , wherein a first simulation has delta values of zero for the total loadings.
11. The computer-readable medium of claim 7 , wherein circuits within each fan-out block are synchronously simulated.
12. The computer-readable medium of claim 7 , further including partitioning at least one fan-out block, designating an other ideal node in that fan-out block, and asynchronously simulating circuits fed by the other ideal node.