Multiple reference phase locked loop
View Patent ↗A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBDIMM system, another may be a forwarded clock in an AMB 2 . A prescaler reduces the frequency of at least the forwarded clock to the lowest common reference frequency which is the frequency of the system reference clock. A PLL at the core of the MPLL may be locked to the forwarded clock or the system reference clock for generating a high speed clock. A feedback divider generates the feedback clock for the PLL as well as other clocks required in the system. Furthermore, the MPLL provides a number of clocking modes, including modes to facilitate testing and powering down of sections of the circuitry for conserving power.
1. A multi reference phase locked loop (MPLL) for generating a high speed clock having a high speed clock frequency and phase locking it to a lowest common reference frequency derived from a selected one of at least two reference clocks, the MPLL comprising:
(a) a prescaler for reducing frequency of at least one of said at least two reference clocks, comprising a first multiplexer for multiplexing the high speed clock and the at least two reference clocks into a multiplexed clock; and a divider circuit for reducing frequency of the multiplexed clock;
(b) a reference selector for selecting the selected one of said at least two reference clocks after its frequency has been reduced in the reference selector to the lowest common reference frequency;
(c) a phase detector for comparing the selected one of the at least two reference clocks with a feedback clock, and generating a frequency control voltage indicative of a phase error between the compared clocks;
(d) a voltage controlled oscillator (VCO) for generating the high speed clock having the high speed clock frequency based on the frequency control voltage until phase locking is indicated by a convergence of the phase error to a substantially constant value; and
(e) a feedback divider for processing the high speed clock into the feedback clock with the same lowest common reference frequency.
2. The system of claim 1 , wherein one of the reference clocks is a forwarded clock, and another of the reference clocks is a system reference clock.
3. The MPLL of claim 1 , wherein the first multiplexer is controlled by a control signal enabling a selection of the forwarded clock.
4. The MPLL of claim 1 , wherein the first multiplexer is controlled by a control signal enabling a selection of the high speed clock.
5. The MALL of claim 1 , further comprising a divider circuit for further reducing the frequency of the multiplexed clock to the lowest common reference frequency.
6. The MPLL of claim 5 , the reference selector further comprising a second multiplexer for selecting the selected one of the at least two reference clocks.
7. The MPLL of claim 5 , further comprising a clock detector for determining a presence of the forwarded clock.
8. The MPLL of claim 7 , further comprising a fail safe logic circuit for controlling the second multiplexer to select the forwarded clock only when its presence is indicated by the clock detector.
9. The MPLL of claim 1 , further comprising:
a digital to analog converter for generating a programmable frequency control voltage; and
an analog multiplexer for alternatively selecting the frequency control voltage and the programmable frequency control voltage to drive the VCO.
10. The MPLL of claim 1 , wherein the feedback divider comprises a plurality of clock dividers for generating clocks, one of which being the feedback clock.
11. A method for generating a high speed clock having a high speed clock frequency and phase locking it to a lowest common reference frequency derived from a selected one of at least two reference clocks, the method comprising:
(a) reducing frequency of at least one of said at least two reference clocks, comprising multiplexing the high speed clock and the at least two reference clocks into a multiplexed clock: and reducing a frequency of the multiplexed clock;
(b) selecting the selected one of said at least two reference clocks after its frequency has been reduced to the lowest common reference frequency;
(c) comparing the selected one of the at least two reference clocks with a feedback clock, and generating a frequency control voltage indicative of a phase error between the compared clocks;
(d) generating the high speed clock having the high speed clock frequency based on the frequency control voltage until phase locking is indicated by a convergence of the phase error to a substantially constant value; and
(e) processing the high speed clock into the feedback clock with the same lowest common reference frequency.
12. The method of claim 11 , wherein one of the reference clocks is a forwarded clock, and another of the reference clocks is a system reference clock.
13. The method of claim 11 , wherein multiplexing comprises enabling a selection of the forwarded clock.
14. The method of claim 11 , wherein multiplexing includes enabling a selection of the high speed clock.
15. The method of claim 11 , further comprising reducing the frequency of the multiplexed clock to the lowest common reference frequency.
16. The method of claim 15 , wherein multiplexing further comprises selecting the selected one of the at least two reference clocks.
17. The method of claim 13 , wherein multiplexing further comprises determining a presence of the forwarded clock in a clock detector.
18. The method of claim 16 , wherein multiplexing further comprises selecting the forwarded clock only when its presence is indicated by the clock detector.
19. The method of claim 11 , further comprising:
generating a programmable frequency control voltage; and
alternatively selecting the frequency control voltage and the programmable frequency control voltage for driving a VCO.
20. The method of claim 11 , further comprising generating clock signals in a plurality of clock dividers, one of the clock signals being the feedback clock.