Patent Assignment
Reel/Frame 035102/0842
Security Interest
Recorded: 2015-03-06
Pages: 12
Assignor
DIABLO TECHNOLOGIES, INC.
Executed: 2015-02-17
Assignee
CITY NATIONAL BANK
200 CLARENDON STREET, 28TH FLOOR, BOSTON, MASSACHUSETTS, 02116
Covered Properties
(24)
Operating Frequency Reduction for Transversal Fir Filter
Fully Adaptive Equalization for High Loss Communications Channels
Receiver-Based Adaptive Equalizer with Pre-Cursor Compensation
Programmable Asynchronous First-in-First-Out (Fifo) Structure with Merging Capability
Voltage Controlled Oscillator (Vco) with a Wide Tuning Range and Substantially Constant Voltage Swing Over the Tuning Range
Linear Phase Interpolator and Phase Detector
Bang-Bang Phase Detector with Sub-Rate Clock
Multiple Reference Phase Locked Loop
Load Reduction Dual in-Line Memory Module (Lrdimm) and Method for Programming the Same
System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System
Load Reduction Dual in-Line Memory Module (Lrdimm) and Method for Programming the Same
System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System
System and Method for Unlocking Additional Functions of a Module
System and Method for Providing an Address Cache for Memory Map Learning
System and Method for Providing a Command Buffer in a Memory System
Load Reduction Dual in-Line Memory Module (Lrdimm) and Method for Programming the Same
System and Method of Implementing an Object Storage Device on a Computer Main Memory System
Application:
14/271,773 →
Publication:
US 2015/0324281
System and Method of Accessing and Controlling a Co-Processor and/or Input/Output Device via Remote Direct Memory Access
Application:
14/271,838 →
Publication:
US 2015/0326684
System and Method for Booting from a Non-Volatile Memory
Application:
14/289,547 →
Publication:
US 2015/0347151
System and Method for Implementing a Multi-Threaded Device Driver in a Computer System
Application:
14/452,473 →
Publication:
US 2016/0041933
System and Method for Mirroring a Volatile Memory of a Computer System
Application:
14/452,477 →
Publication:
US 2016/0041917
Main memory co-processors and input/output devices
Application:
61/457,233 →
System and Method for Offsetting the Data Buffer Latency of a Device Implementing a Jedec Standard Ddr-4 Lrdimm Chipset
Application:
61/968,998 →
System and Method for Providing a Configurable Timing Control for a Memory System
Application:
61/983,386 →
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 14, 2014
From: TAKEFMAN, MICHAEL L; AMER, MAHER; BADELONE, RICCARDO
To: DIABLO TECHNOLOGIES INC.
Reel/Frame 032666/0526 →
Assignment of Assignor's Interest
May 16, 2014
From: TAKEFMAN, MICHAEL L.; TROJANOWSKI, BART; AMER, MAHER
To: DIABLO TECHNOLOGIES INC.
Reel/Frame 032912/0628 →
Assignment of Assignor's Interest
Jan 19, 2017
From: TAKEFMAN, MICHAEL L.; AMER, MAHER; BADALONE, RICCARDO
To: DIABLO TECHNOLOGIES INC.
Reel/Frame 041014/0596 →
Assignment of Assignor's Interest
Jan 23, 2017
From: TAKEFMAN, MICHAEL L; AMER, MAHER; BADALONE, RICCARDO
To: DIABLO TECHNOLOGIES INC.
Reel/Frame 041044/0720 →
Assignment of Assignor's Interest
Jan 23, 2017
From: TAKEFMAN, MICHAEL L.; AMER, MAHER; BADALONE, RICCARDO
To: DIABLO TECHNOLOGIES INC.
Reel/Frame 041044/0571 →
Security Interest
Jun 6, 2017
From: DIABLO TECHNOLOGIES, INC.
To: CITY NATIONAL BANK
Reel/Frame 042619/0675 →
Assignment of Assignor's Interest
Oct 10, 2018
From: DIABLO TECHNOLOGIES INC.
To: RAMBUS INC.
Reel/Frame 047126/0468 →