System and method for providing an address cache for memory map learning
View Patent ↗A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.
1. A method comprising:
providing a one-hot address cache comprising a plurality of one-hot addresses, wherein each one-hot address of the plurality of one-hot addresses has a bit width;
providing a host interface to a host memory controller of a host system,
wherein the one-hot address cache is configured to:
store data associated with a corresponding memory address in an address space of a memory system; and
provide the data to the host memory controller during a memory map learning process, and
wherein the plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and
wherein each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.
2. The method of claim 1 , wherein the bit width is determined based on a bank address length, a row address length and a column address length of the memory system.
3. The method of claim 1 , wherein the bit width is 30 bit.
4. The method of claim 1 , wherein the host memory controller writes first data to a first one-hot address of the one-hot address cache.
5. The method of claim 4 , further comprising:
receiving a read command from the host memory controller at the first one-hot address; and
providing the first data to the host memory controller.
6. The method of claim 1 , further comprising initializing the one-hot address cache with a plurality of registers.
7. The method of claim 1 , further providing the host memory controller with valid data without an error code correction (ECC) error during the memory map learning process.
8. The method of claim 1 , wherein the one hot address cache is configured to have a set of muxes in parallel to a memory of a host-facing buffer manager.
9. The method of claim 8 , further comprising updating the one-hot address cache by a plurality of host writes to the host-facing buffer manager.
10. The method of claim 8 , further comprising:
receiving a read command from the host memory controller at a non-one-hot address; and
providing data from the memory of the host-facing buffer manager.
11. A circuit to receive a command from a host memory controller, the circuit comprising:
a one-hot address cache comprising a plurality of one-hot addresses, wherein each one-hot address of the plurality of one-hot addresses has a bit width;
a host interface to the host memory controller of a host system,
wherein the one-hot address cache is configured to:
store data associated with a corresponding memory address in an address space of a memory system; and
provide the data to the host memory controller during a memory map learning process, and
wherein the plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and
wherein each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.
12. The circuit of claim 11 , wherein the bit width is determined based on a bank address length, a row address length and a column address length of the memory system.
13. The circuit of claim 11 , wherein the bit width is 29 bit.
14. The circuit of claim 11 , wherein the host memory controller writes first data to a first one-hot address of the one-hot address cache.
15. The circuit of claim 14 , wherein the circuit receives a read command from the host memory controller at the first one-hot address and provides the first data to the host memory controller.
16. The circuit of claim 11 , wherein the one-hot address cache is initialized with a plurality of registers.
17. The circuit of claim 11 , wherein the circuit provides the host memory controller with valid data without an error code correction (ECC) error during the memory map learning process.
18. The circuit of claim 11 , further comprising a host-facing memory buffer manager, wherein the one hot address cache is configured to have a set of muxes in parallel to a memory of the host-facing buffer manager.
19. The circuit of claim 18 , wherein the circuit updates the one-hot address cache using a plurality of host writes to the host-facing buffer manager.
20. The circuit of claim 18 , wherein the circuit receives a read command from the host memory controller at a non-one-hot address and provides data from the memory of the host-facing buffer manager.