System and method for unlocking additional functions of a module
View Patent ↗A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode. The maze unlock sequence involves writing a first data pattern of a plurality of data patterns to a memory address of the memory device, reading a first set of data from the memory address, and storing the first set of data in a validated data array. The maze unlock sequence further involves writing a second data pattern of the plurality of data patterns to the memory address, reading a second set of data from the memory address, and storing the second set of data in the validated data array. A difference vector array is generated from the validate data array and an address map of the memory device is identified based on the difference vector array.
1. A method comprising:
operating a memory device in a maze unlock mode;
writing a first data pattern of a plurality of data patterns to a memory address of the memory device;
reading a first set of data from the memory address;
storing the first set of data in a validated data array;
writing a second data pattern of the plurality of data patterns to the memory address;
reading a second set of data from the memory address;
storing the second set of data in the validated data array;
generating a difference vector array from the validated data array; and
identifying an address map of the memory device based on the difference vector array.
2. The method of claim 1 , further comprising generating an array of count values from the difference vector.
3. The method of claim 2 , wherein a count value of the count values indicates a difference between two consecutive validated data in the validated data array.
4. The method of claim 1 , further comprising repeating the writing, reading, and storing until the plurality of data patterns is consumed.
5. The method of claim 1 , wherein the plurality of data patterns comprise 32 data patterns.
6. The method of claim 1 , further comprising running a state machine in the maze unlock mode.
7. The method of claim 6 , wherein the state machine has a plurality of states comprising a single rank alias for discovery state, a single rank alias for BIOS state, a base hunt state, an address hunt state, an address learning state, an ECC, interleave, swizzle learning state, and a full unlock state.
8. A memory module comprising:
a plurality of memory devices; and
a memory control module comprising a maze controller,
wherein the maze controller performs a maze unlock sequence by performing:
operating a memory device of the plurality of memory devices in a maze unlock mode;
writing a first data pattern of a plurality of data patterns to a memory address of the memory device;
reading a first set of data from the memory address;
storing the first set of data in a validated data array;
writing a second data pattern of the plurality of data patterns to the memory address;
reading a second set of data from the memory address;
storing the second set of data in the validated data array;
generating a difference vector array from the validated data array; and
identifying an address map of the memory device based on the difference vector array.
9. The memory module of claim 8 , wherein the maze controller further performs generating an array of count values from the difference vector.
10. The memory module of claim 9 , wherein a count value of the count values indicates a difference between two consecutive validated data in the validated data array.
11. The memory module of claim 8 , wherein the maze controller further performs repeating the writing, reading, and storing until the plurality of data patterns is consumed.
12. The memory module of claim 8 , wherein the plurality of data patterns comprise 32 data patterns.
13. The memory module of claim 8 , wherein the maze controller further performs running a state machine in the maze unlock mode.
14. The memory module of claim 13 , wherein the state machine has a plurality of states comprising a single rank alias for discovery state, a single rank alias for BIOS state, a base hunt state, an address hunt state, an address learning state, an ECC, interleave, swizzle learning state, and a full unlock state.