METAL GATE TRANSISTORS
An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.
1 . An integrated circuit (IC) comprising:
a substrate including first and second active regions;
a first transistor of a first type in the first active region;
a second transistor of a second type in the second active region;
first and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layers of the first and second transistors, wherein the first GTVA layer tunes a gate threshold voltage of the first transistor; and
wherein a channel of the second transistor comprises dopants to tune the gate threshold voltage of the second transistor.
2 . The IC of claim 1 wherein the first type transistor comprises a n type transistor and the second type transistor comprises a p type transistor.
3 . The IC of claim 2 wherein the transistors comprise metal gate electrodes.
4 . The IC of claim 2 comprises a dielectric buffer layer in between the gate dielectric layers and the substrate.
5 . The IC of claim 2 wherein the gate dielectric layers comprise high-k dielectric materials.
6 . The IC of claim 2 comprises a gate electrode buffer layer over metal gate electrodes of the transistors.
7 . The IC of claim 2 wherein the GTVA layers are disposed above, below or a combination thereof the gate dielectric layers.
8 . The IC of claim 2 wherein the GTVA layer comprises lanthanum oxide (LaO).
9 . The IC of claim 1 wherein the transistors comprise metal gate electrodes.
10 . The IC of claim 1 comprises a dielectric buffer layer in between the gate dielectric layers and the substrate.
11 . The IC of claim 1 wherein the gate dielectric layers comprise high-k dielectric materials.
12 . The IC of claim 1 comprises a gate electrode buffer layer over metal gate electrodes of the transistors.
13 . The IC of claim 1 wherein the GTVA layers are disposed above, below or a combination thereof the gate dielectric layers.
14 . The IC of claim 1 wherein the GTVA layer comprises lanthanum oxide (LaO).
15 . The IC of claim 1 wherein the channel of the second transistor comprises p type dopants.
16 . The IC of claim 1 comprises a semiconductor layer on the substrate in the second active region to form the channel of the second transistor.
17 . The IC of claim 16 wherein the semiconductor layer comprises doped SiGe.
18 . The IC of claim 16 wherein the semiconductor layer comprises p-doped SiGe.
19 . A method of forming an IC comprising:
providing a substrate prepared with first and second active regions, wherein a channel region of the second active region comprises a doped channel region;
forming a first transistor of a first type in the first active region; and
forming a second transistor of a second type in the second active region,
wherein first and second transistors include a GTVA adjacent to first and second gate dielectric layers of the first and second transistors, wherein the GTVA layer tunes a gate threshold voltage of the first transistor, and
wherein the second transistor includes a doped channel region to tune a gate threshold voltage of the second transistor.
20 . A method of forming a semiconductor device comprising:
providing a substrate prepared with first and second active regions, wherein a channel region of the second active region comprises a doped channel region;
forming a first transistor of a first type in the first active region; and
forming a second transistor of a second type in the second active region,
wherein first and second transistors include a GTVA adjacent to first and second gate dielectric layers of the first and second transistors, wherein the GTVA layer tunes a gate threshold voltage of the first transistor, and
wherein the second transistor includes a doped channel region comprising a doped semiconductor layer to tune a gate threshold voltage of the second transistor.