Proportional regulation for optimized current sensor performance

1. An integrated circuit device, comprising:

a first transistor having a gate coupled to an output of a first operational amplifier;

a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor;

the second transistor having a gate coupled to an inverting input of a second operational amplifier;

an output of the second operational amplifier coupled to an inverting input of the first operational amplifier;

a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier; and

a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.

2. The integrated circuit of claim 1 , further comprising:

a sense transistor having a gate coupled to the gate of the first transistor;

a third operational amplifier having a first input coupled to a drain of the first transistor and a second input coupled to a drain of the sense transistor; and

a current source controlled by an output of the third operational amplifier.

3. The integrated circuit of claim 1 , wherein a non-inverting input of the first operational amplifier is coupled to a drain of the first transistor.

4. The integrated circuit of claim 1 , wherein a non-inverting input of the second operational amplifier is coupled to the gate of the first transistor.

5. The integrated circuit of claim 1 , wherein the first transistor is a power MOSFET transistor.

6. A controller for a power MOSFET transistor, comprising:

a reference MOSFET transistor having a gate, the reference MOSFET transistor biased to create a voltage at the gate, the gate voltage corresponding to a threshold voltage of the reference MOSFET transistor;

a first amplifier circuit having an input coupled to the reference MOSFET transistor gate via a voltage divider circuit, the voltage divider circuit scaled in proportion to a ratio between a production distribution of a transistor source voltage offset and a production distribution of a transistor threshold voltage mismatch; and

a second amplifier circuit coupled to an output of the first amplifier circuit, the second amplifier circuit having an output adapted to drive a gate of the power MOSFET transistor.

7. The controller of claim 6 , wherein the voltage divider circuit comprises:

a first resistor coupled between the gate of the reference MOSFET transistor and an inverting input of the first amplifier circuit; and

a second resistor coupled between the output of the first amplifier circuit and the inverting input.

8. The controller of claim 7 , wherein the ratio of the second resistor to the first resistor is equivalent to the ratio between a production distribution of a transistor source voltage offset and a production distribution of a transistor threshold voltage mismatch.

9. The controller of claim 6 , wherein the second amplifier circuit has a non-inverting input coupled to a source voltage of the power MOSFET transistor.

10. The controller of claim 6 , wherein the first amplifier circuit has a non-inverting input coupled to a gate voltage of the power MOSFET transistor.

11. The controller of claim 6 , wherein the first amplifier circuit is coupled to an inverting input of the second amplifier circuit.

12. A method of operating a load transistor and a sense transistor in an integrated circuit, the load transistor biased using a gate voltage, the load transistor having a threshold voltage and a drain voltage, and the load transistor having a gate overdrive voltage equal to a difference between the gate voltage and the threshold voltage, comprising:

regulating the biasing of the load transistor so that a ratio of the gate overdrive voltage to the drain voltage equals a ratio of a production distribution of a threshold voltage mismatch to a production distribution of a source voltage offset.

13. The method of claim 12 , wherein the threshold voltage mismatch is a difference between the threshold voltage of the load transistor and a threshold voltage of the sense transistor, and wherein the source voltage offset is a difference between a source voltage of the load transistor and a source voltage of the sense transistor.

14. The method of claim 12 , further comprising:

biasing a reference transistor so that a reference threshold voltage can be detected at a gate of the reference transistor, the reference transistor being proportional to the load transistor and having a smaller area than the load transistor; and

using the reference threshold voltage to control the biasing of the load transistor.

15. An integrated circuit, comprising:

a load transistor biased using a gate voltage, the load transistor having a threshold voltage and a drain voltage, and the load transistor having a gate overdrive voltage equal to a difference between the gate voltage and the threshold voltage;

a sense transistor coupled to the load transistor and configured to measure a current passing through the load transistor; and

a biasing circuit generating a gate voltage for regulating the biasing of the load transistor, the gate voltage selected so that a ratio of the gate overdrive voltage to the drain voltage equals a ratio of a production distribution of a threshold voltage mismatch to a production distribution of a source voltage offset.

16. The integrated circuit of claim 15 , wherein the threshold voltage mismatch is a difference between the threshold voltage of the load transistor and a threshold voltage of the sense transistor, and wherein the source voltage offset is a difference between a source voltage of the load transistor and a source voltage of the sense transistor.

17. The integrated circuit of claim 15 , wherein the biasing circuit further comprises:

a reference transistor proportional to the load transistor and having a smaller area than the load transistor, a reference threshold voltage detectable at a gate of the reference transistor and used to control the biasing of the load transistor.