Semiconductor integrated circuit
View Patent ↗A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal.
1. A semiconductor integrated circuit comprising:
a clock signal generation circuit being inputted into which a first clock signal and a control signal based on an address, and generating a second clock signal based on said first clock signal after a lapse of predetermined time from said input of said control signal,
wherein the predetermined time is no less than one cycle of said first clock signal.
2. The semiconductor integrated circuit according to claim 1 , wherein,
in a first mode, said clock signal generation circuit outputs said second clock signal based on said first clock signal, after being delayed for a first delay time from said control signal; and
in a second mode, said clock signal generation circuit outputs said second clock signal based on said first clock signal, after being delayed for a second delay time from said control signal.
3. The semiconductor integrated circuit according to claim 1 , further comprising:
a control signal controller that outputs said address and said control signal in synchronization with said first clock signal upon receipt of said first clock signal.
4. The semiconductor integrated circuit according to claim 3 , further comprising:
a memory which operates upon receipt of said address, said control signal, and said second clock signal.
5. The semiconductor integrated circuit according to claim 1 , wherein
said clock signal generation circuit outputs a one-shot pulse as said second clock signal.
6. The semiconductor integrated circuit according to claim 1 , wherein
said clock signal generation circuit generates said second clock signal by dividing said first clock signal.
7. The semiconductor integrated circuit according to claim 2 , wherein
said second delay time is greater than said first delay time.
8. The semiconductor integrated circuit according to claim 1 , wherein
said control signal is a chip select signal for selecting a specified circuit from a plurality of circuits to which said second clock signal is to be supplied.
9. The semiconductor integrated circuit according to claim 2 , wherein, in said first mode,
said clock signal generation circuit generates said second clock signal based on a chip select signal, said chip select signals being inputted as said control signal.
10. The semiconductor integrated circuit according to claim 2 , wherein, in said second mode,
said clock signal generation circuit generates said second clock signal based on a chip select signal, a R/W signal indicating a write mode, and a PreWait signal, each of the chip select signals, said R/W signal and said PreWait signal being inputted as said control signal.
11. The semiconductor integrated circuit according to claim 1 , further comprising:
a control signal generation circuit receiving said control signal to assert another control signal for another predetermined time from said input of said control signal,
wherein said predetermined time is shorter than said another predetermined time.
12. The semiconductor integrated circuit according to claim 11 , further comprising:
a latency register holding an externally programmed latency value,
wherein said another predetermined time is determined based on the latency value.
13. A control circuit, comprising:
a control signal generation circuit receiving a first control signal to assert a second control signal for a first period from a first time point in response to the edge of the first control signal; and
a clock generation circuit receiving a first clock signal and being responsive to the first control signal to generate a second clock signal after a second period from the first time point,
wherein the second period is no less than one cycle of the first clock signal and shorter than the first period.
14. The control circuit according to claim 13 , further comprising:
a latency register holding an externally programmed latency value,
wherein the first period is determined based on the latency value.
15. The control circuit according to claim 14 ,
wherein the clock generation circuit does not generate the second clock signal for the second period from the first time point.
16. The control circuit according to claim 15 ,
wherein the clock generation circuit being further responsive to a third control signal indicating a write operation, and
wherein the second period is determined based on the latency value when the third control signal is asserted.