Variability-aware scheme for asynchronous circuit initialization
View Patent ↗A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
1. A method for resetting a desynchronized circuit comprising:
asserting a first reset signal to initialize a control layer;
asserting a second reset signal for initializing a plurality of master-slave sequential elements in the data layer of said desynchronized circuit;
releasing said first reset signal while still asserting said second reset signal in order to activate said control layer and propagate values into at least one sequential element in said data layer;
reasserting said first reset signal to re-initialize said control layer while still asserting said second reset signal;
releasing said second reset signal so as to activate said sequential elements in said data layer; and
releasing said first reset signal for said control layer so as to activate said control layer.
2. The method of claim 1 , wherein said resetting a desynchronized circuit includes resetting at least one data layer circuit and resetting at least one control layer circuit.
3. The method of claim 1 , wherein said initializing a plurality of sequential elements includes initializing at least one of, a latch, a flip-flop, a C-element.
4. A method for resetting a desynchronized circuit comprising:
asserting a first reset signal to initialize a control layer and a second reset signal for initializing a plurality of sequential elements in the data layer of said desynchronized circuit during a first phase;
releasing said first reset signal while still asserting said second reset signal in order to activate said control layer and propagate values in said data layer to reset said data layer during a second phase;
asserting said first reset signal to re-initialize said control layer while still asserting said second reset signal to initialize said data layer of said desynchronized circuit during a third phase;
releasing said second reset signal for said data layer so as to activate said sequential elements in said data layer during a fourth phase; and
releasing said first reset signal for said control layer so as to activate said control layer during a fifth phase, whereby said control layer and said data layer operate normally after releasing said first reset signal.
5. The method of claim 4 , wherein said resetting a desynchronized circuit includes resetting at least one data layer circuit and resetting at least one control layer circuit.
6. The method of claim 4 , wherein said initializing a plurality of sequential elements includes initializing at least one of, a latch, a flip-flop, a C-element.
7. A circuit comprising:
a data circuit for receiving a plurality of inputs and generating a plurality of outputs based on logic of said data circuit;
a control circuit for desynchronizing said data circuit; and
a reset circuit, coupled to said data and control circuits, said reset circuit including:
logic for asserting a first reset signal to initialize the control layer and a second reset signal for initializing a plurality of sequential elements in the data layer of said desynchronized circuit during a first phase;
logic for releasing said first reset signal while still asserting said second reset signal in order to activate said control layer and propagate values in said data layer to reset said data layer during a second phase;
logic for asserting said first reset signal to re-initialize said control layer while still asserting said second reset signal to initialize said data layer of said desynchronized circuit during a third phase;
logic for releasing said second reset signal for said data layer so as to activate said sequential elements in said data layer during a fourth phase; and
logic for releasing said first reset signal for said control layer so as to activate said control layer during a fifth phase, whereby said control layer and said data layer operate normally after releasing said first reset signal.
8. A circuit for resetting a desynchronized circuit comprising:
an input terminal for receiving an external reset signal;
an input terminal for receiving a plurality of control inputs, wherein said plurality of control inputs includes at least one of, a request input, an acknowledge input;
an output terminal for outputting a first reset signal and a second reset signal, and a plurality of control outputs, wherein said plurality of control outputs includes at least one of, a request output, an acknowledge output;
logic for producing said first reset signal and said second reset signal, said first reset signal coupled to at least one control circuit and said second reset signal coupled to at least one data circuit, wherein said logic block is operable for asserting said first reset signal to initialize a control layer and said second reset signal operable for initializing a plurality of sequential elements in a data layer of said desynchronized circuit during a first phase;
logic for releasing said first reset signal while still asserting said second reset signal in order to activate said control layer and propagate values in said data layer to reset said data layer during a second phase;
logic for asserting said first reset signal to re-initialize said control layer while still asserting said second reset signal to initialize said data layer of said desynchronized circuit during a third phase;
logic for releasing said second reset signal for said data layer so as to activate said sequential elements in said data layer during a fourth phase; and
logic for releasing said first reset signal for said control layer so as to activate said control layer during a fifth phase, whereby said control layer and said data layer operate normally after releasing said first reset signal.
9. A method for synthesizing a reset circuit, comprising:
outputting an input terminal for receiving an external reset signal;
an input terminal for receiving a plurality of control inputs, wherein said plurality of control inputs includes at least one of, a request input, an acknowledge input;
outputting an output terminal for outputting a first reset signal and a second reset signal, and a plurality of control outputs, wherein said plurality of control outputs includes at least one of, a request output, an acknowledge output;
outputting logic for producing said first reset signal and said second reset signal, said first reset signal coupled to at least one control circuit and said second reset signal coupled to at least one data circuit, wherein said logic block is operable for asserting said first reset signal to initialize a control layer and said second reset signal operable for initializing a plurality of sequential elements in a data layer of said desynchronized circuit during a first phase;
outputting logic for releasing said first reset signal while still asserting said second reset signal in order to activate said control layer and propagate values in said data layer to reset said data layer during a second phase;
outputting logic for asserting said first reset signal to re-initialize said control layer while still asserting said second reset signal to initialize said data layer of said desynchronized circuit during a third phase;
outputting logic for releasing said second reset signal for said data layer so as to activate said sequential elements in said data layer during a fourth phase; and
outputting logic for releasing said first reset signal for said control layer so as to activate said control layer during a fifth phase, whereby said control layer and said data layer operate normally after releasing said first reset signal.