TEST CIRCUIT
A test circuit includes a plurality of circuit blocks having a same circuit construction and a same function, a plurality of internal test circuits each corresponding to a different one of the plurality of circuit blocks, an OR circuit which outputs a logical sum result of a test result output by each of the plurality of circuit blocks as a first result signal, an AND circuit which outputs a logical product result of the test result output by each of the plurality of circuit blocks as a second result signal, and a decision circuit which outputs a consistent comparison result between the first result signal and the second result signal as a final result signal.
1 . A test circuit comprising:
a plurality of circuit blocks having a same circuit construction and a same function;
a plurality of internal test circuits each corresponding to a different one of the plurality of circuit blocks;
an OR circuit which outputs a logical sum result of a test result output by each of the plurality of circuit blocks as a first result signal;
an AND circuit which outputs a logical product result of the test result output by each of the plurality of circuit blocks as a second result signal; and
a decision circuit which outputs a consistent comparison result between the first result signal and the second result signal as a final result signal.
2 . The test circuit according to claim 1 , wherein the decision circuit includes a XOR circuit which outputs an exclusive OR operation result between the first result signal and the second result signal as the final result signal.
3 . The test circuit according to claim 1 , wherein the plurality of the internal test circuits are scan chain circuits corresponding to each circuit block and a same test pattern is input to each of the plurality of the internal test circuits.
4 . The test circuit according to claim 3 , wherein the same test pattern includes test pattern data, a scan mode control signal, and a scan click signal.
5 . The test circuit according to claim 1 , wherein the plurality of the internal test circuits are Built In Self Test (BIST) circuits corresponding to each circuit block and generate a same test pattern.
6 . The test circuit according to claim 1 , wherein each circuit block outputs at least two test result signals, each corresponding to a different set of test result signals of the plurality of circuit blocks, and a circuit set comprising the OR circuit, the AND circuit and the decision circuit is provided for each set of test result signals.
7 . The test circuit according to claim 6 , wherein the internal test circuit outputs the at least two test result signals.
8 . The test circuit according to claim 6 , wherein each of plurality circuit blocks includes at least two internal test circuits, the at least two internal test circuit each output one of the at least two test result signals, and the circuit set comprising the OR circuit, the AND circuit and the decision circuit is provided for each of the at least two internal test circuits.
9 . The test circuit according to claim 6 , wherein each circuit set corresponds to one test result signal of each of the plurality of circuit blocks, the set of test result signals comprising the one test result signal of each of the plurality of circuit blocks.
10 . The test circuit according to claim 8 , wherein each circuit set corresponds to one test result signal of each of the plurality of circuit blocks, the set of test result signals comprising the one test result signal of each of the plurality of circuit blocks.