Memory cells including nanoporous layers containing conductive material

1. A memory cell comprising:

a first contact having a first surface and an opposing second surface;

a second contact having a first surface and an opposing second surface;

a memory material layer having a first surface and an opposing second surface; and

a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer comprising at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal,

wherein the first surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the opposing second surface of the nanoporous layer is in contact with a surface of the memory material layer.

2. The memory cell according to claim 1 , wherein the memory material layer comprises a resistive random access memory (RRAM) material, a phase change memory (PCM) material, a programmable metallization cell (PMC) material or a spin torque transfer random access memory (STRAM) material.

3. The memory cell according to claim 1 , wherein the nanoporous layer comprises crosslinked polymer.

4. The memory cell according to claim 3 , wherein the nanoporous layer comprises crosslinked polystyrene.

5. The memory cell according to claim 1 , wherein the nanoporous layer comprises alumina (Al 2 O 3 ), zirconia (ZrO 2 ) or titania (TiO 2 ).

6. The memory cell according to claim 1 , wherein the nanoporous layer comprises a plurality of nanopores.

7. The memory cell according to claim 6 , wherein the plurality of nanopores are distributed in a hexagonally arranged pattern.

8. The memory cell according to claim 6 , wherein the dielectric material is continuous in the nanoporous layer and the plurality of nanopores are randomly dispersed throughout the dielectric material.

9. The memory cell according to claim 1 , wherein the at least one nanopore has a diameter from about 2 nm to about 200 nm.

10. The memory cell according to claim 1 , wherein the conductive metal substantially filling the at least one nanopore is chosen from the group consisting of: silver (Ag), copper (Cu), nickel (Ni) gold (Au), platinum (Pt) and palladium (Pd).

11. The memory cell according to claim 1 , wherein the nanoporous layer has a thickness from about 5 nm to about 50 nm.

12. A memory array comprising:

a plurality of memory cells, each memory cell comprising:

a first contact having a first surface and an opposing second surface;

a second contact having a first surface and an opposing second surface;

a memory material layer having a first surface and an opposing second surface; and

a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer comprising at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal,

wherein the first surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second opposing surface of the nanoporous layer is in contact with a surface of the memory material layer;

a plurality of transistors coupled to the plurality of memory cells;

at least one word line; and

at least one bit line,

wherein the word line is generally orthogonal to the bit line and each of the plurality of memory cells are operatively coupled to a word line and a bit line.

13. The memory array according to claim 12 , wherein the memory material layer comprises a resistive random access memory (RRAM) material, a phase change memory (PCM) material, a programmable metallization cell (PMC) material or a spin torque transfer random access memory (STRAM) material.

14. The memory array according to claim 12 wherein the nanoporous layer comprises crosslinked polymer.

15. The memory array according to claim 12 , wherein the nanoporous layer comprises a plurality of nanopores, where each of the plurality of nanopores has a diameter from about 2 nm to about 200 nm.

16. The memory array according to claim 12 , wherein the conductive metal substantially filling the at least one nanopore is chosen from the group consisting of: silver (Ag), copper (Cu), nickel (Ni) gold (Au), platinum (Pt) and palladium (Pd).

17. A method of forming a memory cell comprising the steps of:

forming a first contact layer by depositing a first conductive material on a substrate;

depositing a nanoporous layer on the first contact layer;

creating a plurality of nanopores in the nanoporous layer;

filling the nanopores with a second conductive material;

forming a memory material layer adjacent the nanoporous layer;

forming a second contact layer by depositing a third conductive material on the memory material layer, wherein after the step of creating a plurality of nanopores, the nanoporous layer also comprises a dielectric material.

18. The method of claim 17 , wherein the step of filling the nanopores comprises electrodeposition using the first contact layer as an electrode in the electrodeposition.

19. The method of claim 17 , wherein the step of depositing the nanoporous layer comprises depositing a fourth conductive material and the step of creating the plurality of nanopores comprises anodizing the fourth conductive material to convert it to the dielectric material that contains the nanopores and removing any non-anodized material from the plurality of nanopores.

20. The method of claim 19 , wherein the step of depositing the fourth conductive material further comprises patterning the fourth conductive material with a plurality of defects.

21. The method of claim 17 , wherein the step of depositing the nanoporous layer comprises depositing a diblock copolymer and the step of creating the plurality of nanopores comprises annealing the diblock copolymer under an applied electric field to create cylindrical microdomains, exposing the diblock copolymer to ultra-violet light to degrade a selected number of the cylindrical microdomains, and removing degraded material from the nanopores.