Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
View Patent ↗Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V DS ) of about from about 28 to about 70 volts, a gate to source voltage (V gs ) of from about −3.3 to about −14 volts and a normal operating temperature for at least about 10 hours.
1. A Group III Nitride based field effect transistor (FET) having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V DS ) of from about 28 to about 70 volts and a gate to source voltage (V gs ) of from about −3.3 to about −14 volts for at least about 10 hours.
2. The FET of claim 1 , wherein the FET is operated at a normal operating temperature for at least about 10 hours.
3. The FET of claim 2 , wherein the normal operating temperature is about 140° C.
4. The FET of claim 1 , wherein the FET is operated at a temperature of from about 170 to about 180° C. or hotter.
5. The FET of claim 1 , comprising a GaN channel layer having a thickness less than about 20 μm.
6. The FET of claim 5 , wherein the FET is a high electron mobility transistor (HEMT) and wherein the HEMT further comprises:
an AlN layer on the GaN channel layer;
an AlGaN layer on the AlN layer;
a T- gate contact on the AlGaN layer;
an insulating layer on a surface of the HEMT; and
source and drain contacts on the AlGaN layer.
7. The FET of claim 6 , further comprising a passivation layer on the T-gate contact, the AlGaN layer and the source and drain contacts, the passivation layer including silicon nitride (SiN).
8. The FET of claim 6 having a power density of greater than about 3.0 W/mm operating at a frequency of from about 3.5 to about 4.0 GHz.
9. A Group III Nitride based field effect transistor (FET) capable of withstanding high temperature, reverse bias test conditions of a drain-to-source voltage (V DS ) of from about 28 to about 70 volts and a gate to source voltage (V gs ) of from about −3.3 to about −14 volts for at least about 10 hours.
10. The FET of claim 9 , wherein the FET is operated at a normal operating temperature for at least about 10 hours.
11. The FET of claim 10 , wherein the normal operating temperature is about 140° C.
12. The FET of claim 10 having a power density of greater than about 3.0 W/mm operating at a frequency of from about 3.5 to about 4.0 GHz.
13. The FET of claim 10 , wherein the FET comprises a high electron mobility transistor (HEMT) and wherein the HEMT further comprises:
a GaN channel layer;
an AlN layer on the GaN channel layer;
an AlGaN layer on the AlN layer;
a T- gate contact on the AlGaN layer;
an insulating layer on a surface of the HEMT; and
source and drain contacts on the AlGaN layer.
14. The FET of claim 13 , wherein the GaN channel layer has a thickness of less than about 20 μm.
15. The FET of claim 13 , wherein the insulating layer comprises a passivation layer including silicon nitride (SiN).
16. A high electron mobility transistor (HEMT) having a power degradation of less than about 3.0 dB and a power density of greater than about 3.0 W/mm when operated at a drain-to-source voltage (V DS ) of from about 28 to about 70 volts and a gate to source voltage (V gs ) of from about −3.3 to about −14 volts and for at least about 10 hours.
17. The HEMT of claim 16 , wherein the HEMT is operated at a normal operating temperature for at least about 10 hours.
18. The HEMT of claim 17 , wherein the normal operating temperature is a about 140° C.
19. The HEMT of claim 17 , wherein the HEMT comprises a GaN channel layer having a thickness of less than about 20 μm.
20. The HEMT of claim 17 , wherein the HEMT comprises a passivation layer on a surface of the HEMT, the passivation layer including silicon nitride (SiN).