SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit comprises a first and second common wiring layers common to a plurality of types of products and independent of a user circuit, a customized layer provided between the first common wiring layer and the second common wiring layer and which is configured to form the user circuit. The second common wiring layer is formed above an upper layer of the first common wiring layer, and an universal logic cell is wired to the first and second common wiring layers and the customized layer. A power supply wiring, which is connected to a power supply pad, which is connected to an external power supply, is formed through the second common wiring layer, and the power supply wiring is formed in the same layer as the power supply pad and extends to an internal circuit area in which the universal logic cell is formed.
1 . A semiconductor integrated circuit comprising:
a first common wiring layer common to a plurality of types of products and independent of a user circuit;
a second common wiring layer common to a plurality of types of products and independent of the user circuit, and formed above an upper layer of the first common wiring layer; and
a customized layer provided between the first common wiring layer and the second common wiring layer and which is configured to form the user circuit,
wherein an universal logic cell is wired to the first and second common wiring layers and the customized layer,
wherein a power supply wiring, which is connected to a power supply pad, which is connected to an external power supply, is formed through the second common wiring layer, and
wherein the power supply wiring is formed in the same layer as the power supply pad and extends to an internal circuit area in which the universal logic cell is formed.
2 . The semiconductor integrated circuit according to claim 1 , wherein the power supply wiring is formed in the uppermost layer of the second wiring layer.
3 . The semiconductor integrated circuit according to claim 1 , wherein the second power supply wiring is connected to an internal circuit in the internal circuit area.
4 . The semiconductor integrated circuit according to claim 1 , wherein the semiconductor integrated circuit is formed as a chip, and includes an input/output pad in a peripheral area of a first side of the chip, and the power supply pad is provided in a peripheral area of a second side.
5 . The semiconductor integrated circuit according to claim 1 , wherein the semiconductor integrated circuit is formed as a chip and wherein input/output pads are provided in peripheral areas of a first and second sides of the chip and power supply pads are provided in on third and forth sides of the chip.
6 . The semiconductor integrated circuit according to claim 1 , wherein the semiconductor integrated circuit is formed as a chip, and power supply pads are provided on each of two opposed sides of the chip and are connected by the power supply wiring.
7 . The semiconductor integrated circuit according to claim 1 , wherein a ground wire is formed in the second common wiring layer, is connected to a ground pad, is formed in the same layer as the ground pad and extends to the internal circuit area in which the universal logic cell is formed.
8 . The semiconductor integrated circuit according to claim 7 , wherein the semiconductor integrated circuit is formed as a chip,
wherein the power supply pad is formed in a peripheral area of a first side of the chip, and the ground pad is formed in a peripheral area of second side of the chip, the second side of the chip is opposite the first side of the chip, and
wherein the power supply wire and the ground wire have comb shapes, which are alternatingly interspaced.
9 . The semiconductor integrated circuit according to claim 1 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
10 . The semiconductor integrated circuit according to claim 2 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
11 . The semiconductor integrated circuit according to claim 3 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
12 . The semiconductor integrated circuit according to claim 4 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
13 . The semiconductor integrated circuit according to claim 5 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
14 . The semiconductor integrated circuit according to claim 6 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
15 . The semiconductor integrated circuit according to claim 7 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
16 . The semiconductor integrated circuit according to claim 8 , wherein a wire width of the first common wiring layer is narrower than that of the second common wiring layer.
17 . The semiconductor integrated circuit according to claim 9 , wherein a wire width of the first common wiring layer is less than half of that of the second common wiring layer.