Semiconductor device having polysilicon bit line contact

1. A semiconductor device comprising:

a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other;

a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other;

a source region and a drain region disposed at sides of the floating gate devices;

an insulation layer disposed on the floating gate device and the source region; and

a polysilicon line electrically connected to the drain region.

2. The semiconductor device according to claim 1 , wherein the polysilicon line extends in the word line direction.

3. The semiconductor device according to claim 1 , wherein the polysilicon line is disposed in alternation with the device isolation layers on the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein the polysilicon line contacts the insulation layer on the floating gate device and the source region.

5. The semiconductor device according to claim 1 , wherein the source region is a common source line of an impurity diffusion layer formed through a Self Aligned Source (SAS) process.

6. The semiconductor device according to claim 1 , wherein the floating gate device comprises a tunnel oxide layer, a floating gate, an Oxide-Nitride-Oxide (ONO) layer, and a control gate.

7. The semiconductor device according to claim 1 , further comprising a silicide on the drain region.

8. The semiconductor device according to claim 7 , wherein the polysilicon line contacts the silicide on the drain region.