ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF

1 . A method, comprising:

receiving a first input value at a multiply-addition module;

in response to determining a mode of operation of the multiply-addition module is a first mode:

determining a first operand based on the first input value; and

determining a first arithmetic result based on the first operand value; and

in response to determining the mode of operation of the multiply-addition module is a second mode:

determining a second operand based on a first portion of the first input value;

determining a third operand based on a second portion of the first input value;

determining a second arithmetic result based on the second operand value; and

determining a third arithmetic result based on the third operand value.

2 . The method of claim 1 , further comprising:

receiving a second input value at the multiply-addition module;

in response to determining the mode of operation of the multiply-addition module is the second mode:

determining a fourth operand based on a first portion of the second input value;

determining a fifth operand based on a second portion of the second input value;

wherein determining the second arithmetic result comprises determining the second arithmetic result based on the fourth operand value; and

wherein determining the third arithmetic result comprises determining the third arithmetic result based on the fifth operand value.

3 . The method of claim 2 , wherein determining the second arithmetic result comprises multiplying the second operand by the fourth operand.

4 . The method of claim 3 , wherein determining the third arithmetic result comprises multiplying the third operand by the fifth operand.

5 . The method of claim 2 , wherein:

determining the second arithmetic result comprises using the second operand to determine a first set of partial products and determining the second arithmetic result based on the first set of partial products; and

determining the third arithmetic result comprises using the third operand to determine a second set of partial products and determining the second arithmetic result based on the second set of partial products.

6 . The method of claim 5 , wherein:

determining the second arithmetic result comprises using the second input value to determine the first set of partial products; and

determining the third arithmetic result comprises using the second input value to determine the second set of partial products.

7 . The method of claim 1 , wherein:

the first input value is an N-bit value, where N is an integer;

the first operand is an N-bit value;

the second operand is an M-bit value;

the third operand is a P-bit value, where P plus M is less than N.

8 . The method of claim 1 , wherein:

determining the second arithmetic result comprises receiving an output value from the multiply-addition module and determining the second arithmetic result based on a first portion of the output value; and

determining the third arithmetic result comprises determining the third arithmetic result based on a second portion of the output value.

9 . A method, comprising:

receiving a first value at a multiply-addition module in response to a first instruction;

in response to determining the first instruction is associated with a first precision type [double precision]:

determining the first value represents a single operand; and

determining a first arithmetic result based on the single operand; and

in response to determining the first instruction is associated with a second precision type [single precision]:

determining the first value represents a first plurality of operands comprising a first operand and a second operand;

determining a second arithmetic result based on the first operand; and

determining a third arithmetic result based on the second operand.

10 . The method of claim 9 , further comprising:

receiving a second value at the multiply-addition module;

in response to determining the first instruction is associated with a second precision type [single precision]:

determining the second value represents a second plurality of operands comprising a third operand and a fourth operand;

wherein determining the second arithmetic result comprises determining the second arithmetic result based on the third operand value; and

wherein determining the third arithmetic result comprises determining the third arithmetic result based on the fourth operand value.

11 . The method of claim 10 , wherein determining the second arithmetic result comprises multiplying the first operand by the third operand.

12 . The method of claim 11 , wherein determining the third arithmetic result comprises multiplying the second operand by the fourth operand.

13 . The method of claim 10 , wherein:

determining the second arithmetic result comprises using the first operand to determine a first set of partial products and determining the second arithmetic result based on the first set of partial products; and

determining the third arithmetic result comprises using the second operand to determine a second set of partial products and determining the second arithmetic result based on the second set of partial products.

14 . The method of claim 13 , wherein:

determining the second arithmetic result comprises using the second value to determine the first set of partial products; and

determining the third arithmetic result comprises using the second value to determine the second set of partial products.

15 . The method of claim 9 , wherein:

the first value is an N-bit value, where N is an integer;

the first operand is an M-bit value;

the second operand is a P-bit value, where P plus M is less than N.

16 . The method of claim 9 , wherein:

determining the second arithmetic result comprises receiving an output value from the multiply-addition module and determining the second arithmetic result based on a first portion of the output value; and

determining the third arithmetic result comprises determining the third arithmetic result based on a second portion of the output value.

17 . A device comprising:

a first register configured to store a first input value;

a multiply-addition module comprising:

a first input configured to receive a mode indicator signal;

a second input coupled to the first register;

an output, wherein the multiply-addition module is configured to:

in response to the mode indicator signal indicating a first mode:

determining a first operand based on the first input value; and

provide a first arithmetic result at the output based on the first operand; and

in response to the mode indicator signal indicating a second mode:

determining a second operand based on a first portion of the first input value;

determining a third operand based on a second portion of the first input value;

determining a second arithmetic result based on the second operand; and

provide a third arithmetic result at the output based on the third operand.

18 . The device of claim 17 , further comprising:

a second register configured to store a second input value; and

wherein the multiply-addition module includes a third input coupled to the second register and is configured to:

in response to in response to the mode indicator signal indicating the second mode:

determine a fourth operand based on a first portion of the second input value;

determine a fifth operand based on a second portion of the second input value;

provide the second arithmetic result at the output based on the fourth operand; and

provide the third arithmetic result at the output based on the fifth operand.

19 . The device of claim 18 , wherein the multiply-addition module is configured to determine the second arithmetic result comprises multiplying the second operand by the fourth operand.

20 . The device of claim 18 , wherein:

the first input value is an N-bit value, where N is an integer;

the first operand is an N-bit value;

the second operand is an M-bit value; and

the third operand is a P-bit value, where P plus M is less than N.