Dynamically partitioned CAM array
A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
1. A content addressable memory (CAM) device, comprising:
a comparand register having inputs to receive a search key;
a CAM array including a plurality of individually selectable sub-arrays, each sub-array including a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein each control circuit has an input to receive a corresponding sub-array enable signal; and
partition logic having an input to receive a partition select signal and configured to generate the sub-array enable signals in response to the partition select signal, wherein the control circuits selectively propagate the search key through the sub-arrays of the CAM array in response to the sub-array enable signals, and wherein for each sub-array, if its sub-array enable signal is asserted, its control circuit propagates the search key received from a previous sub-array to the rows of CAM cells in the sub-array for a compare operation.
2. The CAM device of claim 1 , wherein each sub-array is independently enabled for the compare operation in response to its corresponding sub-array enable signal.
3. The CAM device of claim 1 , wherein if the sub-array enable signal is asserted, the control circuit pre-charges the match lines of the sub-array for the compare operation.
4. The CAM device of claim 1 , wherein for each sub-array, if its sub-array enable signal is de-asserted, its control circuit does not propagate the search key to the CAM cells of the sub-array for the compare operation.
5. The CAM device of claim 4 , wherein if the sub-array enable signal is de-asserted, the control circuit does not pre-charge the match lines of the sub-array for the compare operation.
6. The CAM device of claim 1 , wherein each control circuit comprises:
a driver circuit having data outputs connected to a set of comparand lines in the corresponding sub-array, having data inputs connected to a set of comparand lines in the previous sub-array, and having a control input to receive the corresponding sub-array enable signal, wherein the set of comparand lines in each sub-array are connected to corresponding columns of CAM cells in the sub-array.
7. The CAM device of claim 6 , wherein the driver circuit in a first sub-array has data inputs to receive the search key from the comparand register, has data outputs connected to the set of comparand lines in the first sub-array, and is configured to selectively drive the search key onto the set of comparand lines in the first sub-array in response to a first sub-array enable signal.
8. The CAM device of claim 6 , wherein for each sub-array, its driver circuit selectively propagates the search key received from the set of comparand lines in the previous sub-array onto the set of comparand lines of the sub-array in response to the corresponding sub-array enable signal.
9. The CAM device of claim 8 , wherein for each sub-array, each of the comparand lines comprises a comparand line and a complementary comparand line pair that provides a search key bit and its logical complement, respectively, to the corresponding column of CAM cells in the sub-array, and wherein if the corresponding sub-array enable signal is de-asserted, its driver circuit maintains both the comparand line and the complementary comparand line in a logic low state.
10. The CAM device of claim 6 , wherein each control circuit further comprises:
a number of match line pre-charge circuits, each match line pre-charge circuit coupled between a supply voltage and one of the match lines of the corresponding sub-array, having a first input to receive a pre-charge clock signal, and having a second input to receive the corresponding sub-array enable signal.
11. The CAM device of claim 10 , wherein for each sub-array, the match line pre-charge circuits selectively pre-charge their sub-array's match lines upon assertion of the pre-charge clock signal in response to the corresponding sub-array enable signal.
12. A content addressable memory (CAM) device, comprising:
a comparand register having inputs to receive a search key
a CAM array including a plurality of individually selectable sub-arrays, each sub-array including a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein each control circuit has an input to receive a corresponding sub-array enable signal; and
partition logic having an input to receive a partition select signal and configured to generate the sub-array enable signals in response to the partition select signal, wherein the control circuits selectively propagate the search key through the sub-arrays of the CAM array in response to the sub-array enable signals, wherein the partition select signal identifies a number of CAM sub-arrays to be partially disabled for a compare operation, and wherein for each partially disabled sub-array, the sub-array's control circuit propagates the search key received from a previous sub-array to a next sub-array, and maintains the match lines of the partially disabled sub-array in a discharged state.
13. A content addressable memory (CAM) device, comprising:
a comparand register having inputs to receive a search key;
a CAM array including a number of individually selectable sub-arrays, each sub-array comprising:
a plurality of CAM cells arranged in any number of rows and columns, wherein each row of CAM cells is coupled to a match line;
a set of comparand lines, each comparand line coupled to a corresponding column of CAM cells in the sub-array; and
a driver circuit having data outputs connected to the set of comparand lines in the sub-array, having data inputs connected to the set of comparand lines in a previous sub-array, and having a control input to receive a corresponding sub-array enable signal; and
partition logic having an input to receive a partition select signal and configured to generate the sub-array enable signals in response to the partition select signal.
14. The CAM device of claim 13 , wherein each sub-array is independently enabled for a compare operation in response to its corresponding sub-array enable signal.
15. The CAM device of claim 13 , wherein the search key is selectively propagated from the comparand register through the sub-arrays of the CAM array in response to the sub-array enable signals.
16. The CAM device of claim 13 , wherein for each sub-array, its driver circuit selectively propagates the search key received from the comparand lines in the previous sub-array onto the comparand lines of the sub-array in response to the corresponding sub-array enable signal.
17. The CAM device of claim 13 , wherein for each sub-array, if the corresponding sub-array enable signal is asserted, its driver circuit propagates the search key received from the previous sub-array onto the comparand lines of the sub-array, and if the corresponding sub-array enable signal is de-asserted, its driver circuit maintains the comparand lines of the sub-array in an indeterminate state.
18. The CAM device of claim 17 , wherein for each sub-array, each of the comparand lines comprises a complementary comparand line pair that provides a search key bit and its logical complement to the corresponding column of CAM cells in the sub-array, wherein if the corresponding sub-array enable signal is de-asserted, its driver circuit maintains both the comparand lines in a logic low state.
19. The CAM device of claim 13 , wherein each sub-array further comprises:
a number of match line pre-charge circuits, each match line pre-charge circuit coupled between a supply voltage and a match line of a corresponding row of CAM cells of the sub-array, having a first input to receive a pre-charge clock signal, and having a second input to receive the corresponding sub-array enable signal.
20. The CAM device of claim 19 , wherein for each sub-array, the match line pre-charge circuits selectively pre-charge their sub-array's match lines upon assertion of the pre-charge clock signal in response to the corresponding sub-array enable signal.
21. The CAM device of claim 19 , wherein for each sub-array, if the corresponding sub-array enable signal is asserted, the match line pre-charge circuits pre-charge their sub-array's match lines to logic high prior to the compare operation, and if the corresponding sub-array enable signal is de-asserted, the match line pre-charge circuits maintain their sub-array's match lines in a logic low state indicative of a mismatch condition.
22. The CAM device of claim 19 , wherein the partition select signal identifies a number of sub-arrays to be partially disabled for the compare operation.
23. The CAM device of claim 22 , wherein for each partially disabled sub-array, the sub-array's driver circuit propagates the search key received from a previous sub-array to a next sub-array, and the match line pre-charge circuits do not charge the match lines of the rows of CAM cells in the sub-array.
24. A content addressable memory (CAM) device, comprising:
a CAM array having a plurality of individually selectable sub-arrays, each sub-array including a number of rows of CAM cells and including a control circuit, wherein each row of CAM cells is connected to a same address decoder via a corresponding word line and is connected to a same priority encoder via a corresponding match line, wherein each control circuit has an input to receive a corresponding sub-array enable signal that indicates whether the sub-array is to be enabled or disabled for compare operations; and
partition logic having an input to receive a partition select signal and configured to generate the sub-array enable signals in response to the partition select signal; and
a comparand register having inputs to receive a search key and having outputs coupled to the CAM array, wherein during compare operations, the search key is selectively propagated from the comparand register sequentially through the sub-arrays in response to the sub-array enable signals.
25. The CAM device of claim 24 , wherein the partition select signal identifies a number of the sub-arrays to be partially disabled for the compare operation.
26. The CAM device of claim 25 , wherein for each partially disabled sub-array, the sub-array's control circuit propagates the search key received from a previous sub-array to a next sub-array, and maintains the match lines of the partially disabled sub-array in a discharged state.
27. The CAM device of claim 24 , wherein each sub-array further comprises a set of comparand lines, each comparand line coupled to the CAM cells in a corresponding column of the sub-array, and each control circuit further comprises:
a driver circuit having data outputs connected to the set of comparand lines in the sub-array, having data inputs connected to the set of comparand lines in a previous sub-array, and having a control input responsive to the corresponding sub-array enable signal.
28. The CAM device of claim 27 , wherein for each sub-array, its driver circuit selectively propagates the search key received from the comparand lines in the previous sub-array onto the comparand lines of the sub-array in response to the corresponding sub-array enable signal.
29. The CAM device of claim 27 , wherein for each CAM sub-array, if the corresponding sub-array enable signal is asserted, its driver circuit propagates the search key received from the previous CAM sub-array onto the comparand lines of the sub-array, and if the corresponding sub-array enable signal is de-asserted, its driver circuit maintains the comparand lines of the sub-array in an indeterminate state.
30. The CAM device of claim 29 , wherein for each CAM sub-array, each of the comparand lines comprises a complementary comparand line pair that provide a search key bit and its logical complement to the corresponding column of CAM cells in the sub-array, wherein if the corresponding sub-array enable signal is de-asserted, its driver circuit maintains both the comparand lines in a logic low state.
31. The CAM device of claim 27 , wherein each control circuit further comprises:
a number of match line pre-charge circuits, each match line pre-charge circuit coupled between a supply voltage and the match line of a corresponding row of the sub-array, having a first input to receive a pre-charge clock signal, and having a second input to receive the corresponding sub-array enable signal.
32. The CAM device of claim 31 , wherein for each sub-array, the match line pre-charge circuits selectively pre-charge their sub-array's match lines upon assertion of the pre-charge clock signal in response to the corresponding sub-array enable signal.
33. The CAM device of claim 24 , wherein for each sub-array, if the corresponding sub-array enable signal is asserted, the sub-array's control circuit pre-charges the match lines of the rows of CAM cells in the sub-array and propagates the search key received from a previous sub-array to the rows of CAM cells in the sub-array for the compare operation.
34. The CAM device of claim 33 , wherein for each sub-array, if the corresponding sub-array enable signal is de-asserted, the sub-array's control circuit does not pre-charge the match lines of the rows of CAM cells in the sub-array and does not propagate the search key received from a previous sub-array to the rows of CAM cells in the sub-array for the compare operation.
35. A method of minimizing power consumption during a compare operation between a search key and data stored in a content addressable memory (CAM) array having a plurality of individually selectable sub-arrays each including one or more rows of CAM cells coupled to corresponding match lines, the method comprising:
providing the search key to the CAM array;
generating a plurality of sub-array enable signals in response to a partition select signal that indicates which of the sub-arrays are to be enabled for the compare operation; and
selectively propagating the search key through the sub-arrays in response to the sub-array enable signals, wherein the selectively propagating comprises, for each sub-array:
if the corresponding sub-array enable signal is asserted, driving the search key received from a previous sub-array onto a set of comparand lines of the sub-array; and
if the corresponding sub-array enable signal is de-asserted, driving the set of comparand lines of the sub-array to an indeterminate state.
36. The method of claim 35 , further comprising:
selectively pre-charging the match lines of each sub-array in response to its sub-array enable signal.
37. A method of minimizing power consumption during a compare operation between a search key and data stored in a content addressable memory (CAM) array having a plurality of individually selectable sub-arrays each including one or more rows of CAM cells coupled to corresponding match lines, the method comprising:
providing the search key to the CAM array;
generating a plurality of sub-array enable signals in response to a partition select signal that indicates which of the sub-arrays are to be enabled for the compare operation:
selectively propagating the search key through the sub-arrays in response to the sub-array enable signals; and
partially disabling one of the sub-arrays, wherein the partially disabling comprises:
driving the search key received from a previous sub-array to a next sub-array via the set of comparand lines of the partially disabled sub-array; and
maintaining the match lines of the partially disabled sub-array in a discharged state to prevent the CAM cells of the partially disabled sub-array from participating in the compare operation.
38. An apparatus for minimizing power consumption during a compare operation between a search key and data stored in a content addressable memory (CAM) array including a plurality of individually selectable sub-arrays each including one or more rows of CAM cells coupled to corresponding match lines, the apparatus comprising:
means for providing the search key to the CAM array;
means for generating a plurality of sub-array enable signals in response to a partition select signal that indicates which of the sub-arrays are to be enabled for the compare operation; and
means for selectively propagating the search key through the sub-arrays in response to the sub-array enable signals, wherein the means for selectively propagating comprises, for each sub-array:
means for driving the search key received from a previous sub-array onto a set of comparand lines of the sub-array if the corresponding sub-array enable signal is asserted; and
means for driving the set of comparand lines of the sub-array to an indeterminate state if the corresponding sub-array enable signal is de-asserted.
39. The apparatus of claim 38 , further comprising:
means for selectively pre-charging the match lines of each sub-array in response to its sub-array enable signal.
40. An apparatus for minimizing power consumption during a compare operation between a search key and data stored in a content addressable memory (CAM) array including a plurality of individually selectable sub-arrays each including one or more rows of CAM cells coupled to corresponding match lines, the apparatus comprising:
means for providing the search key to the CAM array;
means for generating a plurality of sub-array enable signals in response to a partition select signal that indicates which of the sub-arrays are to be enabled for the compare operation;
means for selectively propagating the search key through the sub-arrays in response to the sub-array enable signals; and
means for partially disabling one of the sub-arrays, wherein the partially disabling comprises:
means for driving the search key received from a previous sub-array to a next sub-array via the set of comparand lines of the partially disabled sub-array; and
means for maintaining the match lines of the partially disabled sub-array in a discharged state to prevent the CAM cells of the partially disabled sub-array from participating in the compare operation.