Light sensor located above an integrated circuit
A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.
1. A method for forming a light sensor located above an integrated circuit comprising the steps of:
forming an integrated circuit comprising at its upper surface a first insulating component;
depositing a second insulating layer;
creating a cavity across the thickness of the second insulating layer;
depositing a metal in the cavity to form a lower electrode having an upper surface such that the lower electrode's upper surface is planar wit the second insulating layer;
depositing an amorphous silicon layer such that the amorphous silicon layer contacts the entire upper surface of the lower electrode;
depositing a doped silicon layer; and
depositing an upper electrode layer.
2. The method of claim 1 , wherein the amorphous silicon layer is a lightly-doped amorphous silicon layer.
3. The method of claim 1 , wherein the cavity has a width that is less than 3 μm.
4. A method of forming a light-emitting diode which is adapted to be integrated wit an integrated circuit, the method comprising:
providing an integrated circuit including a first insulating layer;
depositing a second insulating layer over the first insulating layer, the second insulating layer having an upper surface;
creating a cavity within the second insulating layer;
depositing at least one material in the cavity such that an upper surface of the at least one material is substantially planar with the upper surface of the second insulating layer surrounding the cavity, the at least one material including at least one conductive material;
depositing a first amorphous silicon layer over the second insulating layer such that the first amorphous silicon layer contacts the entire upper surface of the at least one material;
depositing a second amorphous silicon layer over the first amorphous silicon layer; and
depositing an electrode over the second amorphous silicon layer.
5. The method of claim 4 , wherein depositing at least one material in the cavity comprises depositing at least one material including a metal.
6. The method of claim 4 , wherein depositing at least one material in the cavity comprises depositing at least one material including titanium nitride.
7. The method of claim 4 , wherein depositing at least one material in the cavity comprises depositing at least one conductive material in the cavity such that the conductive material is directly in electric contact with a conductive area of the integrated circuit.
8. The method of claim 4 , wherein depositing the first amorphous silicon layer comprises depositing a lightly-doped silicon layer.
9. The method of claim 4 , wherein depositing at least one material in the cavity comprises depositing a metal and a heavily-doped silicon layer.
10. The method of claim 4 , wherein depositing the first amorphous silicon layer comprises depositing an undoped amorphous silicon layer with a thickness between 0.35 μm and 1.3 μm.
11. The method of claim 4 , wherein depositing the second amorphous silicon layer comprises depositing a doped amorphous silicon layer with a thickness between 10 nm and 30 nm, and having a boron concentration of great than 10 18 atoms/cm 3 .
12. The method of claim 4 , wherein depositing the electrode comprises depositing an ITO layer with a thickness of approximately 80 nm.
13. The method of claim 4 , wherein creating the cavity comprises creating a cavity having a square shape.