Pad in semicondcutor device and fabricating method thereof
View Patent ↗A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to N th intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to N th intermediate metal layers are serially connected. Accordingly, the pad reduces total parasitic capacitance components by connecting MIM type capacitors in series, and not necessarily overlapping with each other, thereby minimizing design errors attributed to the pad by reducing parasitic factors generated from the integrated circuit design. The pad may also minimize capacitance attributed to resonance at a specific frequency. Moreover, the pad avoids affecting an adjacent pad or circuit without additional processing, despite maintaining the above-mentioned effects, thereby reducing cost.
1. A pad in a semiconductor device, comprising:
a) an uppermost metal layer in an area of the pad; and
b) first to N th (where N is a positive integer equal to or greater than 2) sequential intermediate metal layers below the uppermost metal layer, comprising the N th intermediate metal layer and an (N-1) th intermediate metal layer, the N th intermediate metal layer having an N th plurality of discontinuous, horizontally spaced apart sub-layers and the (N-1) th intermediate metal layer comprising an (N-1) th plurality of discontinuous, horizontally spaced apart sub-layers, wherein portions of the N th plurality of sub-layers overlap portions of the (N-1) th plurality of sub-layers to form a plurality of serially connected vertical capacitors.
2. The pad of claim 1 , wherein the N th plurality of sub-layers are under an outermost edge of the uppermost metal layer.
3. The pad of claim 2 , wherein N≧3, and an (N-2) th intermediate metal layer is within an area enclosed by the N th intermediate metal layer, the (N-2) th intermediate metal layer having an (N-2) th plurality of discontinuous, horizontally spaced apart sub-layers.
4. The pad of claim 3 , wherein N≧4, and the (N-3) th intermediate metal layer comprises an (N-3) th plurality of discontinuous, horizontally spaced apart sub-layers under the (N-2) th plurality of sub-layers, the (N-3) th sub-layers alternately overlapping with the (N-2) th plurality of sub-layers in a vertical direction, and wherein the sub-layers that vertically overlap with each other configure or form upper and lower capacitor electrodes.
5. The pad of claim 2 , wherein N≧5, wherein an (N-4) th intermediate metal layer having an (N-4) th plurality of discontinuous, horizontally spaced apart sub-layers forms a capacitor by vertically overlapping with the (N-3) th plurality of sub-layers, and wherein the (N-4) th plurality of sub-layers does not vertically overlap with any intermediate metal layer over the (N-3) th plurality of sub-layers.
6. The pad of claim 2 , wherein one of the N th plurality of sub-layers is connected to the uppermost metal layer by a first via.
7. The pad of claim 6 , wherein one of the (N-1) th plurality of sub-layers is connected to the N th intermediate metal layer by a second via.
8. The pad of claim 1 , further comprising a lowermost conductive layer.
9. The pad of claim 8 , wherein the lowermost conductive layer comprises a semiconductor substrate.
10. The pad of claim 1 , wherein each of the vertical capacitors comprises a dielectric layer.
11. The pad of claim 10 , wherein the dielectric layer comprises Si 3 N 4 and/or SiO 2 .
12. The pad of claim 1 , wherein the serially connected vertical capacitors and the first to N th intermediate metal layers configure or form a spiral inductor.
13. The pad of claim 12 , wherein the spiral inductor has a shape selected from the group consisting of a tetragon, an octagon, and a circle.
14. A pad in a semiconductor device, comprising:
a) an uppermost metal layer in an area of the pad; and
b) a plurality of stacked metal layers below the uppermost metal layer, comprising an N th intermediate metal layer having an N th plurality of discontinuous, horizontally spaced apart sub-lavers and an (N-1) th intermediate metal layer comprising an (N-1) th plurality of discontinuous, horizontally spaced apart sub-layers, wherein the N th and the (N-1) th intermediate metal layers form a plurality of serially connected vertical capacitors.
15. The pad of claim 14 , wherein portions of the N th plurality of sub-layers overlap portions of the (N-1) th plurality of sub-layers to form the plurality of serially connected vertical capacitors.
16. The pad of claim 14 , wherein the N th plurality of sub-layers are under an outermost edge of the uppermost metal layer.
17. The pad of claim 16 , wherein N≧3, wherein an (N-2) th intermediate metal layer is within an area enclosed by the N th intermediate metal layer, the (N-2) th intermediate metal layer having an (N-2) th plurality of discontinuous, horizontally spaced apart sub-layers.
18. The pad of claim 17 , wherein N≧4, wherein an (N-3) th intermediate metal layer comprises an (N-3) th plurality of discontinuous, horizontally spaced apart sub-layers under the (N-2) th plurality of sub-layers, alternately overlapping with the (N-2) th plurality of sub-layers in the vertical direction, and the sub-layers that vertically overlap with each other configure or form upper and lower capacitor electrodes.
19. The pad of claim 18 , wherein N≧5, wherein an (N-4) th intermediate metal layer having an (N-4) th plurality of discontinuous, horizontally spaced apart sub-layers forms a capacitor by vertically overlapping with the (N-3) th plurality of sub-layers, and the (N-4) th plurality of sub-layers does not vertically overlap with any intermediate metal layer over the (N-3) th plurality of sub-layers.
20. The pad of claim 14 , wherein one of the N th plurality of sub-layers is connected to the uppermost metal layer by a first via, and one of the (N-1) th plurality of sub-layers is connected to the N th intermediate metal layer by a second via.