DATA PROCESSING APPARATUS AND DATA PROCESSING SYSTEM
Decrease in throughput performance called a “jamming” in a memory device is prevented. There is provided a timing generation part which gives, based on a request signal outputted for each unit of the data processing from a data processing part, an output timing for a burst transfer request to a burst transfer request generation part. Based on the relationship in size between a lapsed time from the output of the burst transfer request to the activation of the request signal and a time specified by a set threshold value of a threshold value register, the timing generation part controls output timing for a burst transfer request. When the lapsed time exceeds the time specified by a maximum threshold value, the burst transfer request generation part is given an output timing for the burst transfer request without waiting for the activation of the request signal. As a result, when the issuance of the request signal is delayed, a next burst transfer request can be given to the memory device without waiting for the issuance but preceding it.
1 . A data processing apparatus comprising:
a data processing part which performs data processing by using data sequentially read from a memory device;
a burst transfer request generation part which outputs a burst transfer request to the memory device in order to read data sequentially; and
a timing generation part which gives an output timing for the burst transfer request to said burst transfer request generation part based on a request signal outputted for each unit of the data processing from the data processing part,
wherein, when a lapsed time from the output of said burst transfer request to the activation of said request signal exceeds the time specified by the set value of a threshold value register, said timing generation part gives the output timing for the burst transfer request to said burst transfer request generation part without waiting for the activation of the request signal.
2 . A data processing apparatus according to claim 1 , comprising a control part which can read from and write to said threshold value register.
3 . A data processing apparatus comprising:
a data processing part which performs data processing by using data sequentially read from a memory device;
a burst transfer request generation part which outputs a burst transfer request to the memory device in order to read data sequentially; and
a timing generation part which gives an output timing for the burst transfer request to said burst transfer request generation part based on a request signal outputted for each unit of the data processing from the data processing part,
wherein, when a lapsed time from the output of said burst transfer request to the activation of said request signal is shorter than the time specified by the set value of a first threshold value register, after the lapsed time specified by the set value of said first threshold value register, said timing generation part gives an output timing for the burst transfer request to said burst transfer request generation part.
4 . A data processing apparatus according to claim 3 , wherein, when the lapsed time from the output of said burst transfer request to the activation of said request signal exceeds the time specified by the set value of a second threshold value register, said timing generation part gives an output timing for a burst transfer request to said burst transfer request generation part without waiting for the activation of said request signal.
5 . A data processing apparatus according to claim 4 , comprising a control part which can read from and write to said first and second threshold value registers.
6 . A data processing apparatus according to claim 5 , wherein said data processing part is a CODEC which codes and decodes image data and is formed over a single semiconductor substrate.
7 . A data processing system comprising:
a memory device;
a first data processing apparatus capable of accessing said memory device; and
a second data processing apparatus capable of accessing said memory device,
wherein said first data processing apparatus comprises: a data processing part which performs data processing by using data sequentially read from said memory device; a burst transfer request generation part which outputs a burst transfer request to the memory device in order to read data sequentially; and a timing generation part which gives an output timing for the burst transfer request to said burst transfer request generation part based on a request signal outputted for each processing unit of the data processing from said data processing part; and
wherein, when a lapsed time from the output of said burst transfer request to the activation of said request signal exceeds the time specified by the set value of a threshold value register, said timing generation part gives the output timing for the burst transfer request to said burst transfer request generation part without waiting for the activation of said request signal.
8 . A data processing system comprising: a memory device; a first data processing apparatus capable of accessing said memory device; and a second data processing apparatus capable of accessing said memory device,
wherein said first data processing apparatus comprises: a data processing part which performs data processing by using data sequentially read from said memory device; a burst transfer request generation part which outputs a burst transfer request to the memory device in order to read data sequentially; and a timing generation part which gives an output timing for the burst transfer request to said burst transfer request generation part based on a request signal outputted for each processing unit of the data processing from said data processing part; and
wherein, when a lapsed time from the output of said burst transfer request to the activation of said request signal is shorter than the time specified by the set value of a first threshold value register, said timing generation part gives an output timing for the burst transfer request to said burst transfer request generation part after the lapsed time specified by the set value of said first threshold value register.
9 . A data processing system according to claim 8 , wherein, when the lapsed time from the output of said burst transfer request to the activation of said request signal exceeds the time specified by the set value of a second threshold value register, said timing generation part gives an output timing for a burst transfer request to said burst transfer request generation part without waiting for the activation of said request signal.
10 . A data processing system according to claim 9 , wherein, when the lapsed time from the output of said burst transfer request to the activation of said request signal exceeds the time specified by the set value of the first threshold value register and is shorter than the time specified by the set value of the second threshold value register, said timing generation part gives an output timing for a burst transfer request to said burst transfer request generation part in synchronism with the activation of said request signal.