Electrically programmable and erasable memory device and method of fabrication thereof
View Patent ↗The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
1. A method of forming a memory device comprising:
providing a substrate;
providing a tunneling layer over the substrate;
providing a floating gate over the tunneling layer, the floating gate comprising a plurality of electrons;
providing a dielectric over the floating gate, wherein providing the dielectric over the floating gate comprises:
depositing a first insulating layer over the floating gate, the first insulating layer being formed by depositing a silicon dioxide layer over the floating gate,
depositing a second insulating layer comprising a silicon oxynitride layer over the first insulating layer,
depositing a third insulating layer comprising a silicon nitride layer over the second insulating layer;
providing a control gate over the dielectric; and
providing a source and a drain in the substrate,
wherein the source and the drain are in contact with opposite sides of a bottom surface of the tunneling layer,
wherein, the memory device is electrically erased by applying a positive voltage to the control gate and the drain while holding the source at ground and allowing the substrate to float, the positive voltage being of sufficient magnitude to eliminate a barrier presented by the second insulating layer, and to reduce barriers presented by the first and third insulating layers,
wherein the positive voltage provides a plurality of holes in the control gate with sufficient energy to overcome a valence energy level of the first and third insulating layers, and to cause the plurality of holes to travel through the first, second, and third insulating layers,
further wherein, a conductive energy level of the second insulating layer is higher than a conductive energy level of the third insulating layer.
2. The method of claim 1 wherein the providing control gate over the dielectric comprises forming a polysilicon layer over the dielectric.
3. The method of claim 1 and further comprising forming the silicon oxynitride layer by undertaking nitridation of a portion of the silicon dioxide layer.
4. The method of claim 3 wherein the undertaking nitridation of a portion of the silicon dioxide layer is performed by a nitrogen-containing plasma treatment.
5. The method of claim 1 and further comprising forming the silicon oxynitride layer by depositing an additional silicon dioxide layer on the first insulating layer, and undertaking nitridation of the additional silicon dioxide layer.
6. The method of claim 5 wherein undertaking nitridation of the additional silicon dioxide layer is performed by a nitrogen-containing plasma treatment.
7. The method of claim 1 and further comprising forming the silicon oxynitride layer by depositing a silicon nitride layer on the first insulating layer, and undertaking oxidation of the silicon nitride layer.
8. The method of claim 1 wherein forming the silicon oxynitride layer comprises implanting a portion of the silicon dioxide layer with nitrogen.
9. The method of claim 8 and further comprising forming the silicon oxynitride layer by undertaking an anneal step.
10. The method of claim 1 wherein forming the silicon oxynitride layer comprises depositing an additional silicon dioxide layer on the first insulating layer, and implanting the additional silicon dioxide layer with nitrogen.
11. The method of claim 10 and further comprising forming the silicon oxynitride layer by undertaking an anneal step.
12. The method of claim 1 wherein forming the silicon oxynitride layer comprises depositing a silicon nitride layer on the first insulating layer, and implanting the silicon nitride layer with oxygen.
13. The method of claim 12 and further comprising forming the silicon oxynitride layer by undertaking an anneal step after said implantation.
14. The method of claim 1 wherein forming the silicon oxynitride layer comprises depositing alternate silicon nitride and silicon dioxide monolayers on the first insulating layer.
15. The method of claim 14 and further comprising forming the silicon oxynitride layer by undertaking an anneal step after said deposition of alternate silicon nitride and silicon dioxide monolayers.
16. The method of claim 1 , wherein a valence energy level of the second insulating layer is lower than the valence energy level of the third insulating layer when the positive voltage pulse is not being applied to the control gate.