Semiconductor integrated circuit device having control circuit to selectively activate decoupling cells

1. A semiconductor integrated circuit device, comprising:

a plurality of decoupling cells that suppress power noise respectively;

a plurality of power switches that connect the plurality of decoupling cells to a power line respectively; and

a control circuit that controls a number of power switches selected from among the plurality of power switches to be turned on according to a level of the power noise that changes according to an operation state of an internal circuit driven by a power supplied from the power line,

wherein the control circuit includes a resonance frequency calculation circuit that calculates a resonance frequency according to a parasitic component of a package and the operation state of the internal circuit, and

wherein the control circuit controls the number of power switches selected from among the plurality of power switches and to be turned on according to the resonance frequency and a frequency of a clock signal.

2. The semiconductor integrated circuit device according to claim 1 , wherein the control circuit includes a memory that stores the frequency of the clock signal and a value of the parasitic component of the package.

3. A semiconductor integrated circuit device, comprising:

a plurality of decoupling cells that suppress power noise respectively;

a plurality of power switches that connect the plurality of decoupling cells to a power line respectively; and

a control circuit that controls a number of power switches selected from among the plurality of power switches to be turned on according to a level of the power noise that changes according to an operation state of an internal circuit driven by a power supplied from the power line,

wherein the control circuit includes a measurement circuit that measures the power noise, and

wherein the control circuit changes the number of power switches to be turned on according to the level of the power noise measured by the measurement circuit.

4. The semiconductor integrated circuit device according to claim 3 , wherein the control circuit increases the number of power switches to be turned on if the level of the power noise measured by the measurement circuit is greater than a preset reference value.

5. The semiconductor integrated circuit device according to claim 3 , wherein the control circuit decreases the number of power switches to be turned on if the level of the power noise measured by the measurement circuit increases after the number of on-state power switches increases.

6. A control circuit, comprising:

a resonance frequency calculator which calculates a resonance frequency;

a determination circuit which compares the resonance frequency with a clock frequency for driving a logic circuit for a comparison result; and

an optimal status calculation circuit, responsive to the comparison result of the determination circuit, which decides a difference value between the resonance frequency from the resonance frequency calculator and the clock frequency, wherein the difference value controls a number of decoupling cells being activated.

7. A control circuit, comprising:

a measurement circuit which measures a noise on a power source line;

a comparison circuit which compares the measured noise with a noise previously measured or a predetermined level; and

a controller which controls of decoupling cells being activated based on a comparison result.

8. The control circuit as claimed in claim 7 , further comprising:

a resonance frequency calculator which calculates a resonance frequency; and a determination circuit which compares the resonance frequency with a clock frequency of a clock signal for driving a logic circuit; and

an optimal status calculation circuit, responsive to a result of the determination circuit, to decide a difference value between the resonance frequency and the clock frequency, wherein the result of the determination circuit controls the activated amount number of decoupling cells.

9. The control circuit as claimed in claim 8 , further comprising: a memory which stores the clock frequency of the clock signal and a value of a parasitic component of a package sealing the logic circuit.

10. The control circuit as claimed in claim 8 , wherein the measurement circuit, the comparison circuit, the controller, the resonance frequency calculator, the determination circuit, the logic circuit, and the optimal status calculation circuit are integrated as an integrated circuit,

wherein the resonance frequency calculator receives a value of a parasitic component of a package sealing the integrated circuit, inputted from an outside of the integrated circuit.

11. The control circuit as claimed in claim 10 , wherein the determination circuit receives the clock frequency of the clock signal, inputted from an outside of the integrated circuit.