Semiconductor integrated circuit having output buffer circuit

1 . A semiconductor integrated circuit, comprising:

a semiconductor substrate;

wells formed on the semiconductor substrate;

at least one output buffer transistor formed in the wells;

at least one well tap provided to correspond to the output buffer transistor;

a first power supply line connected to a source electrode of the output buffer transistor; and

a second power supply line connected to the well tap, the first power supply line and the second power supply line being separately provided in different paths.

2 . A semiconductor integrated circuit, comprising:

a semiconductor substrate;

wells formed on the semiconductor substrate;

a plurality of output buffer transistors formed in at least a part of the wells;

a plurality of well taps provided to respectively correspond to the plurality of output buffer transistors;

a first power supply line connected in common to source electrodes of the plurality of output buffer transistors; and

a second power supply line connected in common to the plurality of well taps, the first power supply line and the second power supply line being separately provided in different paths,

wherein the first power supply line and the second power supply line are each connected to a common power supply.

3 . The semiconductor integrated circuit according to claim 1 , wherein:

the at least one output buffer transistor comprises a plurality of output buffer transistors, and the at least one well tap comprises a plurality of well taps respectively corresponding to the plurality of output buffer transistors;

the first power supply line is connected in common to source electrodes of the plurality of output buffer transistors; and

the second power supply line is connected in common to the plurality of well taps.

4 . The semiconductor integrated circuit according to claim 1 , wherein the first power supply line and the second power supply line are each connected to a common power supply.

5 . The semiconductor integrated circuit according to claim 1 , wherein:

the semiconductor substrate has transistors other than the output buffer transistor, formed thereon; and

at least a part of the transistors are formed in one of the well having the output buffer transistor formed therein, and the well electrically connected to the well having the output buffer transistor formed therein, via the semiconductor substrate.

6 . The semiconductor integrated circuit according to claim 2 , wherein:

the semiconductor substrate has transistors other than the output buffer transistor, formed thereon; and

at least a part of the transistors are formed in one of the well having the output buffer transistor formed therein, and the well electrically connected to the well having the output buffer transistor formed therein, via the semiconductor substrate.

7 . The semiconductor integrated circuit according to claim 1 , wherein the semiconductor substrate and the wells have the same conductivity type.

8 . The semiconductor integrated circuit according to claim 2 , wherein the semiconductor substrate and the wells have the same conductivity type.

9 . The semiconductor integrated circuit according to claim 1 , further comprising an internal core region formed on the semiconductor substrate,

wherein the first power supply line and the second power supply line are each formed to extend around the internal core region.

10 . The semiconductor integrated circuit according to claim 2 , further comprising an internal core region formed on the semiconductor substrate,

wherein the first power supply line and the second power supply line are each formed to extend around the internal core region.

11 . The semiconductor integrated circuit according to claim 1 , wherein the first power supply line and the second power supply line are formed so as to be spaced apart from each other to sufficiently reduce mutual inductance and coupling capacity therebetween.

12 . The semiconductor integrated circuit according to claim 2 , wherein the first power supply line and the second power supply line are formed so as to be spaced apart from each other to sufficiently reduce mutual inductance and coupling capacity therebetween.

13 . The semiconductor integrated circuit according to claim 1 , further comprising a noise filter connected to the second power supply line.

14 . The semiconductor integrated circuit according to claim 2 , further comprising a noise filter connected to the second power supply line.

15 . The semiconductor integrated circuit according to claim 1 , further comprising:

a first power supply pad connected to the first power supply line; and

a second power supply pad connected to the second power supply line,

wherein the first power supply pad and the second power supply pad are formed on the semiconductor substrate, and are connected to each other outside the semiconductor substrate.

16 . The semiconductor integrated circuit according to claim 2 , further comprising:

a first power supply pad connected to the first power supply line; and

a second power supply pad connected to the second power supply line,

wherein the first power supply pad and the second power supply pad are formed on the semiconductor substrate, and are connected to each other outside the semiconductor substrate.

17 . The semiconductor integrated circuit according to claim 1 , further comprising a power supply pad connected in common to the first power supply line and the second power supply line,

wherein the first power supply line and the second power supply line are lines branched from the power supply pad.

18 . The semiconductor integrated circuit according to claim 2 , further comprising a power supply pad connected in common to the first power supply line and the second power supply line,

wherein the first power supply line and the second power supply line are lines branched from the power supply pad.