Multi-valued mask ROM

1. A mask ROM comprising:

a plurality of memory cells each including:

first and second nodes; and

a transistor including a source and drain connected to said first and second nodes, respectively,

wherein a first memory cell out of said plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between said first and second nodes,

wherein a resistance of said first resistive interconnection is adjusted depending on data stored onto said first memory cell,

wherein a second memory cell out of said plurality of memory cells further includes a second resistive interconnection which provides an electrical connection between said first and second nodes of said second memory cell, and

wherein said resistance of said first resistive interconnection is different from a resistance of said second resistive interconnection.

2. The mask ROM according to claim 1 , wherein material of said first resistive interconnection is same as that of a gate electrode of said first memory cell.

3. The mask ROM according to claim 2 , wherein said first resistive interconnection is formed of material selected from a group consisting of polysilicon, amorphous silicon, and silicon germanium.

4. The mask ROM according to claim 1 , wherein a width of said first resistive interconnection is different from a width of said second resistive interconnection.

5. The mask ROM according to claim 1 , wherein said first resistive interconnection is formed between a gate layer in which a gate electrode of said transistor is formed and a metal interconnection layer in which a metal interconnection is formed.

6. The mask ROM according to claim 1 , wherein said mask ROM and an EEPROM are monolithically integrated within a single semiconductor chip, said EEPROM including a control gate and a floating gate,

wherein said control gate is formed to be opposed to said floating gate across a dielectric film,

wherein a gate electrode of said transistor is formed in a same layer as said floating gate, and

wherein said first resistive interconnection is formed in a same layer as said control gate.

7. The mask ROM according to claim 1 , wherein, when data stored in a selected memory cell out of said plurality of memory cells are read, said transistor of said selected memory cell is turned off.

8. The mask ROM according to claim 1 , wherein said plurality of memory cells are arranged to form a NAND type mask ROM.

9. The mask ROM according to claim 8 , wherein when data stored in a selected memory cell out of said plurality of memory cells is read, said transistor of said selected memory cell is turned off and said transistors of remaining memory cells out of said plurality of memory cells are turned on.

10. The mask ROM according to claim 1 , wherein the first resistive interconnection comprises a structure in a NAND type cell and is connected to the first and second nodes in parallel with the transistor.

11. The mask ROM according to claim 1 , wherein a thickness of the first resistive interconnection is substantially same as a thickness of the second resistive interconnection, where the first resistive interconnection and the second resistive interconnections are formed concurrently.

12. The mask ROM according to claim 1 , wherein a third memory cell of the plurality of memory cells further includes a third resistive interconnection which provides an electrical connection between said first and second nodes of said third memory cell, and

wherein said resistance of said first resistive interconnection and said resistance of said second resistive interconnection is different from a resistance of said third resistive interconnection.

13. A mask ROM comprising:

a plurality of memory cells each including:

first and second nodes; and

a transistor including a source and drain connected to said first and second nodes, respectively,

wherein a first memory cell out of said plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between said first and second nodes,

wherein a resistance of said first resistive interconnection is adjusted depending on data stored onto said first memory cell, and

wherein a width of the first resistive interconnection is less than a width of the transistor.