IP Library Granted Patent US 7,750,681
Granted Patent B2
US 7,750,681 · App. 12/285,375 · Granted Jul 6, 2010

Semiconductor integrated circuit

Assignee: Sony Corporation
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Quick Facts
Patent No.
US 7,750,681
App. No.
12/285,375
Granted
Jul 6, 2010
Kind
B2
Abstract

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Claims (19)

1. A semiconductor integrated circuit comprising:

a main-interconnect to which supply voltage or reference voltage is applied;

a plurality of sub-interconnects;

a plurality of circuit cells configured to be connected to the plurality of sub-interconnects;

a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and

an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

2. The semiconductor integrated circuit according to claim 1 , wherein

the main-interconnect is disposed along a direction perpendicular to the plurality of sub-interconnects, and

the auxiliary interconnect is disposed in parallel to the main-interconnect, and is connected to the plurality of sub-interconnects at intersections of the auxiliary interconnect and the plurality of sub-interconnects.

3. The semiconductor integrated circuit according to claim 2 , wherein

a plurality of the power supply switch cells are disposed on a line along the same direction as the direction along which the main-interconnect is disposed, and are connected to a plurality of control lines in accordance with a predetermined connection rule.

4. The semiconductor integrated circuit according to claim 1 , wherein

the main-interconnect and the plurality of sub-interconnects are disposed along the same direction in parallel to each other, and

the auxiliary interconnect is disposed perpendicular to the main-interconnect, and is connected to the plurality of sub-interconnects at intersections of the auxiliary interconnect and the plurality of sub-interconnects.

5. The semiconductor integrated circuit according to claim 4 , wherein

a plurality of the power supply switch cells are disposed on a line along a direction perpendicular to the direction along which the main-interconnect is disposed, and are connected to a plurality of control lines in accordance with a predetermined connection rule.

6. The semiconductor integrated circuit according to claim 5 , wherein

two of the sub-interconnects are disposed on both sides of the main-interconnect along a width direction of the main-interconnect, and

the two sub-interconnects are controlled by different ones of the control lines.

Assignments (2)
CHANGE OF NAME Recorded Sep 13, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 057493/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2008
From: OGATA, HIROMI
To: SONY CORPORATION
Reel/Frame 021706/0292 →
Priority Claims (1)
JP 2007-289250 · Nov 7, 2007 · national
Continuity (1)
Related Publication 20090115394A1 · May 7, 2009