Programmable matrix array with chalcogenide material
View Patent ↗A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.
1. An integrated circuit, comprising: a first conductive line; a second conductive line; a controllable interconnect device coupled between said first and second conductive lines; a control circuit for controlling the state of said interconnect device, said control circuit including an SRAM device, said SRAM device comprising a threshold switching material.
2. An integrated circuit, comprising: a first conductive line; a second conductive line; a controllable interconnect device coupled between said first and second conductive lines; an SRAM device coupled to said interconnect device, said SRAM device comprising a threshold switching material.
3. The integrated circuit of claim 2 , wherein said SRAM device comprises a first inverter cross-coupled with a second inverter.
4. The integrated circuit of claim 3 , wherein said first inverter comprises a first transistor in series with a first load and said second inverter comprises a second transistor in series with a second load.
5. The integrated circuit of claim 4 , wherein said first load includes a first phase-change memory element and said second load includes a second phase-change memory element.
6. The integrated circuit of claim 4 , wherein said first load include a first threshold switching element and said second load includes a second threshold switching element.
7. The integrated circuit of claim 4 , wherein said first load includes a first threshold switching element in series with a first phase-change memory element and said second load includes a second threshold switching element in series with a second phase-change memory element.
8. The integrated circuit of claim 3 , wherein said first inverter comprises a first phase-change memory element and said second inverter comprises a second phase-change memory element.
9. The integrated circuit of claim 3 , wherein said first inverter comprises a first threshold switching element and said second inverter comprises a second threshold switching element.
10. The integrated circuit of claim 3 , wherein said first inverter comprises a first threshold switching element in series with a first phase-change memory element and said second inverter comprises a second threshold switching element in series with a second phase-change memory element.
11. The integrated circuit of claim 2 , wherein said SRAM device further comprises a first transistor cross-coupled with a second transistor.
12. The integrated circuit of claim 11 , wherein said SRAM device further comprises a first phase-change memory element in series with said first transistor and a second phase-change memory element in series with said second transistor.
13. The integrated circuit of claim 11 , wherein said SRAM device further comprises a first threshold switching element in series with said first transistor and a second threshold switching element in series with said second transistor.
14. The integrated circuit of claim 2 , wherein said SRAM device further comprises a first phase-change memory element series with a first threshold switching element and a second phase-change memory element in series with a second threshold switching element.
15. The integrated circuit of claim 2 , wherein said interconnect device includes a transistor.
16. The integrated circuit of claim 15 , wherein said transistor is coupled between said first conductive line and said second conductive line.
17. The integrated circuit of claim 16 , wherein said transistor is a MOS transistor.
18. The integrated circuit of claim 2 , wherein said controllable interconnect device is a controllable impedance device.
19. The integrated circuit of claim 2 , wherein said interconnect device is a controllable switch.
20. The integrated circuit of claim 2 , wherein said interconnect device is a silicon controlled rectifier.
21. The integrated circuit of claim 2 , wherein said first conductive line crosses said second conductive line.
22. The integrated circuit of claim 2 , wherein said first conductive line is one of a plurality of first conductive lines of a matrix array and said second conductive line is one of a plurality of second conductive lines of said matrix array.
23. The integrated circuit of claim 2 , wherein said integrated circuit is a programmable logic device.