Content addressable memory (CAM) cell having column-wise conditional data pre-write
View Patent ↗A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.
1. A content addressable memory (CAM) device including a plurality of CAM cells arranged in rows and columns to form multi-byte words, each CAM cell comprising:
a comparator circuit coupled between a match line and a first voltage node having at least a first switch device;
a first data storing circuit including a first write circuit coupled to a first internal node of the comparator circuit that writes a logic level at the first voltage node into the first data storing circuit; and
a second data storing circuit including a second write circuit coupled to a second internal node of the comparator circuit that writes the logic level at the first voltage node into the second data storing circuit; wherein
the first switch device is enabled in a write operation to at least the first data storing circuit, and selectively enabled in response to compare data in a compare operation.
2. The CAM device of claim 1 , wherein:
the comparator circuit comprises a first controllable impedance path coupled between the match line and the first voltage node and a second controllable impedance path coupled between the match line and the first voltage node;
the first write circuit includes a first insulated gate field effect transistor (IGFET) having a source-drain path coupled between one of the controllable impedance paths and a first data storage node in the first data storing circuit and a control gate coupled to a first control signal node; and
the second write circuit includes a second IGFET having a source-drain path coupled between one of the controllable impedance paths and a second data storage node in the second data storing circuit and a control gate coupled to a second control signal node.
3. The CAM device of claim 2 wherein:
the first control signal node and second control signal node are coupled to receive the same control signal.
4. The CAM device of claim 1 , wherein:
the first internal node and the second internal node of the comparator circuit are the same internal node.
5. The CAM device of claim 2 , wherein:
the first controllable impedance path comprises
a first comparator insulated gate field effect transistor (IGFET) having a source-drain path coupled between the match line and a first internal node and a gate coupled to receive data stored in the first data storing circuit and a second comparator IGFET having a source-drain path coupled between the first internal node and the first voltage node and a gate coupled to receive a compare data value; and
the second controllable impedance path comprises
a third comparator IGFET having a source-drain path coupled between the match line and a second internal node and a gate coupled to receive data stored in the second data storing circuit and a fourth comparator IGFET having a source-drain path coupled between the second internal node and the first voltage node and a gate coupled to receive complementary compare data.
6. The CAM device of claim 1 , wherein:
the comparator circuit further includes a second switch device that is enabled in a write operation to the second data storing circuit, and selectively enabled in response to compare data in a compare operation.
7. A content addressable memory (CAM) device including a plurality of CAM cells arranged in rows and columns to form multi-byte words, each CAM cell comprising:
a comparator circuit having at least a first charge transfer path through a first internal node between a match line and a first voltage node that includes a first switch device enabled in response to a first data value;
a first data storing circuit that stores the first data value and includes a first write circuit coupled to the first internal node that writes a logic level at the first voltage node into the first data storing circuit; and
a second data storing circuit including a second write circuit coupled to a second internal node of the comparator circuit that writes the logic level at the first voltage node into the second data storing circuit.
8. The CAM device of claim 7 , wherein:
the comparator circuit further includes a second charge transfer path between a match line and a first voltage node that includes a second switch device enabled in response to a second data value; and
the second data storing circuit stores the second data value.
9. The CAM device of claim 7 , wherein:
the second write circuit is coupled to the second internal node by a second current path.
10. The CAM device of claim 7 , wherein:
the first switch device enables a current path between the match line and the first internal node.
11. The CAM device of claim 7 , wherein:
the first charge transfer path further includes a compare switch device in series with the first switch device that is enabled in response to a compare data value in a compare operation, and enabled in a write operation.
12. The CAM device of claim 11 , wherein:
the compare switch device enables a current path between the first internal node and the first voltage node.