Method and system for manufacturing a semiconductor device having plural wiring layers

1. A method of manufacturing a semiconductor device which has a plurality of wiring layers, comprising:

determining, using a computing device, design criteria, and a manufacturing condition of said semiconductor device;

carrying out layout design of said semiconductor device based on functional specification and said design criteria to produce a layout data;

estimating process variations of width and thickness of each of interconnections for every wiring layer from said layout data based on said design criteria and said manufacturing condition;

determining an interconnection delay affected by a specific condition of said process variations for every wiring layer;

repeating correction of said layout data, the estimation and the determination until the determined interconnection delay meets said function specification, to produce a final layout data; and

manufacturing said semiconductor device based on said final layout data and said manufacture condition,

wherein said determining an interconnection delay comprises:

determining a variation of said interconnection delay by using of parasitic resistance and parasitic capacitance for every wiring layer through statistical relaxation in which the process variations of width and thickness of each of interconnections are independent between said plurality of wiring layers.

2. The method according to claim 1 , wherein said method further comprises:

reading a netlist of an LSI of said semiconductor device;

reading a layout data indicating a layout of said LSI;

calculating a parasitic resistance and a parasitic capacitance for said manufacturing condition to each of a plurality of interconnections contained in said layout by referring to parameters stored in a library; and

generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.

3. The method according to claim 1 , wherein said method further comprises:

reading a netlist of said LSI of said semiconductor device;

reading a layout data indicating a layout of said LSI;

calculating a parasitic resistance and a parasitic capacitance for said manufacturing condition to each of a plurality of interconnections contained in said layout by referring to a center resistance value, a center capacitance value, and ratios β R and β C stored in a library; and

generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.

4. The method according to claim 3 , wherein said calculating comprises:

calculating said parasitic resistance and said parasitic capacitance in said manufacturing condition by multiplying the ratios β R and β C by said center resistance value and said center capacitance value, respectively.

5. The method according to claim 3 , wherein said calculating comprises:

generating correction ratios β R ′ and β C ′ by correcting said ratios β R and β C based on a configuration of a node; and

calculating said parasitic resistance and said parasitic capacitance in said manufacturing condition by multiplying the correction ratios βR′ and β C ′ by said center resistance value and said center capacitance value, respectively.

6. The method according to claim 5 , wherein said node comprises a group of interconnections in each of N interconnection layers (N is a natural number),

a summation of lengths of the interconnections in said group is Li (i is an integer equal to or more than 1 and equal to or smaller than N), and

said ratio β C and said correction ratio β C ′ are the following equation:

β C ′=1+(βC−1)γ C

a parameter γ C satisfies the following equation:

γ

C

=

∑

N

⁢

L

i

2

/

∑

N

⁢

L

i

.

7. The method according to claim 6 , wherein said interconnection groups are connected in series in said node,

said ratio β R and said correction ratio β R ′ are the following equation:

β R ′1+(β R −1)γ R

said parameter γ R satisfies the following equation:

γ

R

=

∑

N

⁢

L

i

2

/

∑

N

⁢

L

i

.

8. The method according to claim 6 , wherein said interconnection groups are branched in said node,

a sub interconnection group in n interconnection layer (n is an integer equal to or more than 1 and equal to or smaller than N) is connected in series to one interconnection in said interconnection group,

a summation of lengths of the interconnections in said sub interconnection group is Lj (j is an integer equal to or more than 1 and equal to or smaller than n), and

said ratio β R and said correction ratio β R ′ to said one interconnection are the following equation:

β R ′=1+(β R −1)γ R

said parameter γ R satisfies the following equation:

γ

R

=

∑

N

⁢

L

j

2

/

∑

N

⁢

L

j

.

9. The method according to claim 8 , wherein when a plurality of said correction ratios β R ′ are calculated to said one interconnection, the largest one of said plurality of correction ratios β R ′ is adopted.

10. The method according to claim 9 , wherein the largest one of a plurality of said correction ratios β C ′ is adopted as a coupling capacitance between said nodes.

11. A system for designing and manufacturing a semiconductor device which has a plurality of wiring layers, comprising:

means for determining design criteria, and a manufacturing condition of said semiconductor device;

means for carrying out layout design of said semiconductor device based on functional specification and said design criteria to produce a layout data;

means for estimating process variations of width and thickness of each of interconnections for every wiring layer from said layout data based on said design criteria and said manufacturing condition;

means for determining an interconnection delay affected by a specific condition of said process variations for every wiring layer;

means for repeating correction of said layout data, the estimation and the determination until the determined interconnection delay meets said function specification, to produce a final layout data; and

means for manufacturing said semiconductor device based on said final layout data and said manufacture condition,

wherein said means for determining an interconnection delay comprises:

means for determining a variation of said interconnection delay by using of parasitic resistance and parasitic capacitance for every wiring layer through statistical relaxation in which the process variations of width and thickness of each of interconnections are independent between said plurality of wiring layers.

12. The system according to claim 11 , further comprising:

means for reading a netlist of an LSI of said semiconductor device;

means for reading a layout data indicating a layout of said LSI;

means for calculating a parasitic resistance and a parasitic capacitance for said manufacturing condition to each of a plurality of interconnections contained in said layout by referring to parameters stored in a library; and

means for generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.

13. The system according to claim 11 , further comprising:

means for reading a netlist of said LSI of said semiconductor device;

means for reading a layout data indicating a layout of said LSI;

means for calculating a parasitic resistance and a parasitic capacitance for said manufacturing condition to each of a plurality of interconnections contained in said layout by referring to a center resistance value, a center capacitance value, and ratios β R and β C stored in a library; and

means for generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.

14. The system according to claim 13 , wherein said means for calculating calculates said parasitic resistance and said parasitic capacitance in said manufacturing condition by multiplying the ratios β R and β C by said center resistance value and said center capacitance value, respectively.

15. The system according to claim 13 , wherein said means for calculating comprises:

means for generating correction ratios β R ′ and β C ′ by correcting said ratios β R and β C based on a configuration of a node; and

means for calculating said parasitic resistance and said parasitic capacitance in said manufacturing condition by multiplying the correction ratios β R ″ and β C ′ by said center resistance value and said center capacitance value, respectively.

16. The system according to claim 15 , wherein said node comprises a group of interconnections in each of N interconnection layers (N is a natural number),

a summation of lengths of the interconnections in said group is Li (i is an integer equal to or more than 1 and equal to or smaller than N), and

said ratio β C and said correction ratio β C ′ are the following equation:

β C ′=1+(β C −1)γ C

a parameter γ C satisfies the following equation:

γ

C

=

∑

N

⁢

L

i

2

/

∑

N

⁢

L

i

.

17. The system according to claim 16 , wherein said interconnection groups are connected in series in said node, and

said ratio β R and said correction ratio β R ′ are the following equation:

β R ′=1+(β R −1)γ R

said parameter γ R satisfies the following equation:

γ

R

=

∑

N

⁢

L

i

2

/

∑

N

⁢

L

i

.

18. The system according to claim 16 , wherein said interconnection groups is branched in said node,

a sub interconnection group in n interconnection layer (n is an integer equal to or more than 1 and equal to or smaller than N) is connected in series to one interconnection in said interconnection group,

a summation of lengths of the interconnections in said sub interconnection group is Lj (j is an integer equal to or more than 1 and equal to or smaller than n), and

said ratio β R and said correction ratio β R ′ to said one interconnection are the following equation:

β R ′=1+(β R −1)γ R

said parameter γ R satisfies the following equation:

γ

R

=

∑

N

⁢

L

j

2

/

∑

N

⁢

L

j

.

19. The system according to claim 18 , wherein when a plurality of said correction ratios β R ′ are calculated to said one interconnection, the largest one of said plurality of correction ratios β R ′ is adopted.

20. The system according to claim 19 , wherein the largest one of a plurality of said correction ratios β C ′ is adopted as a coupling capacitance between said nodes.