Non binary flash array architecture and method of operation
A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array.
1. A non-volatile memory array comprising:
a plurality of Erase Sectors (Esecs) disposed according to a non-binary arrangement; and
an address decoder for determining a physical address of a given Erase Sector (ESec) using modular arithmetic, wherein the physical address includes:
a first pointer (ysel) specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG);
a second pointer (esg) specifying a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and
a third pointer (psec) specifying a given Physical Sector (PSec) within the array.
2. The array according to claim 1 , wherein the array includes a non-binary number of Esecs.
3. The array according to claim 1 , wherein the array includes a non-binary number of Physical Pages (slices).
4. The array according to claim 1 , wherein the array includes a non-binary number of Physical Sectors (PSecs).
5. The array of claim 1 , wherein the array includes a non-binary number of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs).
6. The array of claim 1 , wherein there is a non-binary number of wordlines per Erase Sector Group (ESG).
7. The array of claims 1 , further comprising a pipeline unit for performing the determination in a synchronous pipeline.
8. The array of claim 1 , wherein a physical address of a given memory location within a given Erase Sector (ESec) comprises:
a first pointer specifying a given wordline within the given Erase Sector (ESec); and
a second pointer specifying a given page in the given Erase Sector (Esec).
9. The array of claim 1 , wherein there are a same number of wordlines in each of the Physical Sectors (PSecs).
10. The array of claim 1 , wherein there are 38 Erase Sector Groups (ESGs), 9 Physical Pages (slices) and 24 Physical Sectors (PSecs).
11. A method of addressing cells within a non-volatile memory array including Erase Sectors disposed according to a non-binary arrangement, said method comprising:
using modular arithmetic, translating a first set of addressing bits into a first pointer (ysel) specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); and
using modular arithmetic, translating the first set of addressing bits into a second pointer (esg) specifying a given Erase Sector Group (ESG) within a given Physical Sector (Psec).
12. The method according to claim 11 , further comprising translating the first set of addressing bits into a third pointer (psec) specifying a given Physical Sector (PSec) within the array.
13. The method according to claim 12 , wherein for a given ESec a combination of the first pointer (ysel) specifying the given Erase Sector (ESec) within a given Erase Sector Group (ESG), the second pointer (esg) specifying the given Erase Sector Group (ESG) within a given Physical Sector (Psec) and the third pointer (psec) specifying the given Physical Sector (PSec) within the array define a physical address of the given Erase Sector (ESec).
14. The method of claim 12 , further comprising calculating the third pointer (psec) based on dividing a range of Physical Sectors (PSecs) into a number of equal parts, and assigning each part a Physical Sector number (PSec#=P).
15. The method of claim 14 , further comprising using modular subtraction to perform a number of subtractions, using the number of subtractions as the Physical Sector Number (Psec#), and using a remainder to point to the Erase Sector (ESec) within the identified Physical Sector (PSec).
16. The method of claim 15 , further comprising calculating the first pointer (ysel) and the second pointer (esg) based on dividing a range of Erase Sectors (Esecs) into a number of equal parts, and assigning each part an Erase Sector Group Number (EsecG#); and using modular subtraction to perform a number of subtractions, and using the number of substations as the Erase Sector Group Number (EsecG#), and using a remainder as the value for the ysel pointer to the Physical Page (slice).
17. A non-volatile memory device comprising:
a controller;
a plurality of Erase Sectors (Esecs) disposed according to a non-binary arrangement; and
an address decoder for determining a physical address of a given Erase Sector (ESec), wherein the physical address includes:
a first pointer (ysel) specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG);
a second pointer (esg) specifying a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and
a third pointer (psec) specifying a given Physical Sector (PSec) within the array.
18. A non-volatile memory array comprising:
a plurality of Erase Sectors (Esecs) disposed according to a non-binary arrangement, wherein a physical address of a given memory location within a given Erase Sector (ESec) is determined using modular arithmetic and comprises:
a first pointer specifying a given wordline within the given Erase Sector (ESec); and
a second pointer specifying a given page in the given Erase Sector (Esec).
19. A non-volatile memory device comprising:
a controller; and
a plurality of Erase Sectors (Esecs) disposed according to a non-binary arrangement;
wherein a physical address of a given memory location within a given Erase Sector (ESec) is determined using modular arithmetic and comprises:
a first pointer specifying a given wordline within the given Erase Sector (ESec); and
a second pointer specifying a given page in the given Erase Sector (Esec).