MOS transistor and manufacturing method thereof

1. A method for manufacturing a MOS transistor, comprising:

preparing a substrate, wherein the substrate is a polysilicon substrate;

forming an insulting layer on the substrate, further comprising forming a first insulating layer by implanting ions into a predetermined depth of the substrate and performing a heat treatment;

forming a gate in the insulating layer, wherein a top surface of the gate is exposed, further comprising:

forming the gate by performing a patterning and etching process on the substrate over the first insulating layer; and

forming a second insulating layer to embed the gate of which the top surface is exposed;

forming a gate oxide layer on the insulating layer and the gate;

forming a silicon layer on the gate oxide layer; and

forming a source region and a drain region in the silicon layer on both sides of the gate such that the source and drain regions are in contact with the gate oxide layer.

2. The method according to claim 1 , wherein;

the insulating layer is formed on an entire top surface of the substrate;

the top surface of the gate is not covered by the insulating layer;

a bottom surface of the insulating layer is lower than a bottom surface of the gate;

wherein the gate is formed in a trench in the insulating layer.

3. The method according to claim 1 , wherein forming the gate further comprises:

etching the insulating layer by a predetermined width such that a top surface of the substrate is not exposed; and

forming the gate by depositing polysilicon on the etched insulating layer.

4. The method of claim 1 , wherein

forming the insulating layer further comprises forming the first insulating layer on the substrate by thermal oxidation; and

forming the gate further comprises forming the gate on the first insulting layer by depositing and etching polysilicon.

5. The method according to claim 1 , further comprising, after forming the gate, planarizing the top surface of the insulating layer and the exposed top surface of the gate.

6. A method for manufacturing a MOS transistor, comprising:

preparing a substrate, wherein a gate is embedded in an upper portion of the substrate, and wherein the substrate is a polysilicon substrate, further comprising:

forming a first insulating layer by implanting ions into a predetermined depth of the substrate and performing a heat treatment;

forming the gate by performing a patterning and etching process on the substrate over the first insulating layer; and

forming a second insulating layer to embed the gate of which a top surface is exposed;

forming a silicon layer on which a gate oxide layer is formed;

bonding a top surface of the substrate and a top surface of the silicon layer together; and

forming a source region and a drain region in the silicon layer by implanting impurities such that the source and drain regions are in contact with the gate oxide layer.

7. The method according to claim 6 , wherein preparing the substrate comprises:

forming an insulting layer on the substrate;

etching the insulating layer by a predetermined width such that the top surface of the substrate is not exposed; and

forming the gate by depositing polysilicon on the etched insulating layer.

8. The method according to claim 6 , wherein preparing the substrate comprises:

forming the first insulating layer on the substrate by thermal oxidation; and

forming the gate on the first insulating layer by depositing and etching polysilicon.

9. The method according to claim 6 , wherein bonding the top surface of the substrate and the top surface of the silicon layer together comprises:

provisionally bonding the top surface of the substrate and the top surface of the silicon layer together; and

completely bonding the top surface of the substrate and the top surface of the silicon layer by heating the top surface of the substrate and the top surface of the silicon layer at a predetermined temperature or higher.

10. The method according to claim 6 , wherein:

an insulating layer is formed on the entire top surface of the substrate;

a top surface of the gate is not covered by the insulating layer;

a bottom surface of the insulating layer is lower than a bottom surface of the gate; and

the gate is formed in a trench in the insulating layer.