Embedded DRAM with bias-independent capacitance
View Patent ↗An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.
1. A dynamic random access memory (DRAM) circuit for storing a logic high state or a logic low state comprising:
a p-type semiconductor region;
an n-well located in the p-type semiconductor region;
a p-channel access transistor having a first p-type source/drain region and a second p-type source/drain region located in the n-well;
a capacitor coupled to the second p-type source/drain region of the access transistor, the capacitor including a conductor overlying a portion of the n-well, wherein a p-type oxidation enhancing implant is located below a gate dielectric of the capacitor; and
a wordline driver connected to a gate terminal of the access transistor, the wordline driver being configured to apply a first voltage to the gate terminal of the access transistor when the DRAM circuit is not being accessed, the first voltage being a positive power supply voltage.
2. The DRAM circuit of claim 1 , wherein the wordline driver is further configured to apply a second voltage to the gate terminal of the access transistor when the DRAM circuit is being accessed, the second voltage being less than the threshold supply voltage of the access transistor.
3. The DRAM circuit of claim 2 , wherein the second voltage is in the range of −0.50 to −0.80 Volts.
4. The DRAM circuit of claim 1 , further comprising:
a contact region located in the n-well and spaced apart from the capacitor; and
a positive voltage source connected to the contact region, the positive voltage source supplying a voltage between ½ V dd and V dd .
5. A dynamic random access memory (DRAM) circuit for storing a logic high state or a logic low state, comprising:
an n-type semiconductor region;
a p-well located in the n-type semiconductor region;
an n-channel access transistor having a first n-type source/drain region and a second n-type source/drain region located in the p-well;
a capacitor coupled to the second n-type source/drain region of the access transistor, the capacitor including a conductor overlying a portion of the p-well, and a dielectric, wherein an n-type oxidation enhancing implant is located below said dielectric, and
a wordline driver connected to a gate terminal of the access transistor, the wordline driver being configured to apply a first voltage to the gate terminal of the access transistor when the DRAM circuit is not being accessed, the first voltage being either the ground voltage or a voltage between a negative voltage supply and the ground voltage.
6. The DRAM circuit of claim 5 , wherein the wordline driver is further configured to apply a second voltage to the gate terminal of the access transistor when the DRAM circuit is being accessed, the second voltage being Vdd plus a boosted voltage.
7. The DRAM circuit of claim 6 , wherein the boosted voltage depends on the threshold voltage (V t ) of the access transistor and corresponds to 1.3×V t .
8. The DRAM circuit of claim 5 , further comprising:
a contact region located in the p-well and spaced apart from the capacitor; and
a positive voltage source connected to the contact region, the positive voltage source supplying a voltage between 0 and ½ V dd .
9. dynamic random access memory (DRAM) circuit for storing a logic high state or a logic low state comprising:
a p-type semiconductor region;
an n-well located in the p-type semiconductor region;
a p-channel access transistor having a first p-type source/drain region and a second p-type source/drain region located in the n-well;
a capacitor coupled to the second p-type source/drain region of the access transistor, the capacitor including a conductor overlying a portion of the n-well; and
a wordline driver connected to a gate terminal of the access transistor, the wordline driver being configured to apply a first voltage to the gate terminal of the access transistor when the DRAM circuit is not being accessed, the first voltage being less than a positive power supply voltage.
10. The DRAM circuit of claim 9 , further comprising:
a contact region in the n-well and spaced apart from the capacitor; and
a positive voltage source connected to the contact region, the positive voltage source supplying a voltage between ½ V dd and V dd .
11. The DRAM circuit of claim 9 , further comprising a p-type oxidation enhancing implant below a gate dielectric of the capacitor.