Patent Assignment
Reel/Frame 061593/0094
Release of Security Interest
Recorded: 2022-10-03
Pages: 13
Assignor
PERASO INC. F/K/A MOSYS, INC.
Executed: 2022-10-03
Assignee
INGALLS & SNYDER LLC
1325 AVENUE OF THE AMERICAS, 18TH FLOOR, NEW YORK, NEW YORK, 10019
Covered Properties
(81)
Method and Structure for Improving Display Data Bandwidth in a Unified Memory Architecture System
Patent:
5,790,138 →
Application:
08/587,379 →
Multi-Port Dram Cell and Memory System Using Same
Patent:
5,923,593 →
Application:
08/767,707 →
Memory Cell for Dram Embedded in Logic
Patent:
6,075,720 →
Application:
09/134,488 →
Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory
Patent:
5,999,474 →
Application:
09/165,228 →
Method and Apparatus for Increasing the Time Available for Refresh for 1-T Sram Compatible Devices
Patent:
6,075,740 →
Application:
09/181,840 →
Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same
Patent:
6,415,353 →
Application:
09/405,607 →
Method of Operating a System-on-a-Chip Including Entering a Standby State in a Non-Volatile Memory While Operating the System-on-a-Chip from a Volatile Memory
Patent:
6,457,108 →
Application:
09/415,032 →
Method and Apparatus for Memory Redundancy with No Critical Delay-Path
Patent:
6,732,229 →
Application:
09/503,751 →
Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices
Patent:
6,256,248 →
Application:
09/590,943 →
Method and Apparatus for Forcing Idle Cycles to Enable Refresh Operations in a Semiconductor Memory
Error Correcting Memory and Method of Operating Same
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Sram Emulator
Method of Fabricating a Dram Cell Having a Thin Dielectric Access Transistor and a Thick Dielectric Storage Capacitor
Non-Volatile Memory Cell Fabricated with Slight Modification to a Conventional Logic Process and Methods of Operating Same
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Interleaved Wordline Architecture
Memory System and Memory Device Having a Serial Interface
Method of Encoding and Synchronizing a Serial Interface
Comparator Chain Offset Reduction
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Dual-Port Sram Memory Using Single-Port Memory Cell
Scalable Embedded Dram Array
Word Line Driver for Dram Embedded in a Logic Process
Method to Increase Charge Retention of Non-Volatile Memory Manufactured in a Single-Gate Logic Process
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Comparator Chain Offset Reduction
Scalable Embedded Dram Array
Embedded Dram with Bias-Independent Capacitance
Embedded Dram with Multiple Gate Oxide Thicknesses
Data Restoration Method for a Non-Volatile Memory
Automatic Refresh for Improving Data Retention and Endurance Characteristics of an Embedded Non-Volatile Memory in a Standard Cmos Logic Process
Multi-Bank Multi-Port Architecture
Low Jitter Large Frequency Tuning Lc Pll for Multi-Speed Clocking Applications
Method and Apparatus to Encode and Synchronize a Serial Interface
Multiple Cycle Memory Write Completion
Three State Word Line Driver for a Dram Memory Device
Hierarchical Organization Of Large Memory Blocks
High Utilization Multi-Partitioned Serial Memory
Hierarchical Multi-Bank Multi-Port Memory Organization
Reducing Latency in Serializer-Deserializer Links
Communication Interface and Protocol
Memory Device Including a Memory Block Having a Fixed Latency Data Output
Signal Alignment System
Method of forming a MIM capacitor
Semiconductor Chip Layout
Voltage-Mode Driver with Equalization
Equalization Circuit
Low Power Serial to Parallel Converter
Method and Apparatus for Restoring Data in a Non-Volatile Memory
Programmable Test Engine (Pcdte) for Emerging Memory Technologies
Memory System Including Variable Write Command Scheduling
Separate Pass Gate Controlled Sense Amplifier
Methods for Accessing Dram Cells Using Separate Bit Line Control
System with Logic and Embedded Mim Capacitor
Data Synchronization For Circuit Resources Without Using A Resource Buffer
Multiple Cycle Memory Write Completion
Reducing Latency in Serializer-Deserializer Links
Memory System Including Variable Write Command Scheduling
Integrated Circuit Package with Segregated Tx and Rx Data Channels
Delay-Locked Loop with Phase Adjustment
Methods and Circuits for Adjusting Parameters of a Transceiver
Memory Device with Background Built-in Self-Testing and Background Built-in Self-Repair
Pseudo-Supply Hybrid Driver
Programmable Memory Built in Self Repair Circuit
Traffic Metering and Shaping for Network Packets
Application:
13/838,971 →
Publication:
US 2013/0329553
Memory with Bank-Conflict-Resolution (Bcr) Module Including Cache
Semiconductor Chip Layout with Staggered Tx and Tx Data Lines
Memory System Including Variable Write Burst and Broadcast Command Scheduling
Dual Counter
Application:
13/911,999 →
Publication:
US 2013/0329555
Programmable Partitionable Counter
Hybrid Driver Including a Turbo Mode
Hierarchical Multi-Bank Multi-Port Memory Organization
Substitute Redundant Memory
Delay-Locked Loop with Dual Loop Filters for Fast Response and Wide Frequency and Delay Range
Application:
14/231,730 →
Publication:
US 2014/0218083
Delay-Locked Loop with Independent Phase Adjustment of Delayed Clock Output Pairs
Memory Device with Background Built-in Self-Repair Using Background Built-in Self-Testing
Hybrid Driver Circuit
Method and Apparatus for Randomizer
Integrated Main Memory And Coprocessor With Low Latency
Application:
14/872,002 →
Publication:
US 2016/0188222
Integrated Main Memory and Coprocessor with Low Latency
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.