Methods for accessing DRAM cells using separate bit line control
View Patent ↗A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.
1. A method of accessing a dynamic random access memory (DRAM) cell comprising:
driving a first bit line and a second bit line to a pre-charge voltage; then
ceasing to drive the first bit line to the pre-charge voltage, and enabling a DRAM cell coupled to the first bit line, thereby developing a read voltage on the first bit line;
continuing to drive the second bit line to the pre-charge voltage while the read voltage is developing on the first bit line; and then
ceasing to drive the second bit line to the pre-charge voltage, and enabling a sense amplifier coupled to the first and second bit lines, whereby the sense amplifier drives the first bit line to a first supply voltage and the second bit line to a second supply voltage in response to the read voltage on the first bit line.
2. The method of claim 1 , wherein the step of driving the first and second bit lines to the pre-charge voltage comprises:
driving a first global bit line and a second global bit line to the pre-charge voltage;
electrically connecting the first global bit line to the first bit line; and
electrically connecting the second global bit line to the second bit line.
3. The method of claim 2 , wherein the step of ceasing to drive the first bit line to the pre-charge voltage comprises electrically isolating the first bit line from the first global bit line.
4. The method of claim 3 , wherein the step of ceasing to drive the second bit line to the pre-charge voltage comprises electrically isolating the second bit line from the second global bit line.
5. The method of claim 1 , wherein the step of enabling the sense amplifier comprises:
driving a first power supply terminal of the sense amplifier from the pre-charge voltage to the first supply voltage; and
driving a second power supply terminal of the sense amplifier from the pre-charge voltage to the second supply voltage.
6. The method of claim 1 , further comprising:
pre-charging a first global bit line and a second global bit line to the pre-charge voltage; and then
after the sense amplifier has driven the first bit line to the first supply voltage, coupling the first bit line to the first global bit line, thereby developing a global read voltage on the first global bit line; and
electrically isolating the second bit line from the second global bit line while the global read voltage is developed on the first global bit line.
7. The method of claim 6 , further comprising enabling a global sense amplifier coupled to the first and second global bit lines after developing the global read voltage on the first global bit line, whereby the global sense amplifier drives the first global bit line to the first supply voltage and the second global bit line to the second supply voltage in response to the global read voltage on the first global bit line.
8. The method of claim 6 , wherein the pre-charge voltage is between the first supply voltage and the second supply voltage.
9. The method of claim 1 , further comprising:
pre-charging a first global bit line and a second global bit line to the pre-charge voltage; and then
after the sense amplifier has driven the second bit line to the second supply voltage, coupling the second bit line to the second global bit line, thereby developing a global read voltage on the second global bit line; and
electrically isolating the first bit line from the first global bit line while the global read voltage is developed on the second global bit line.
10. The method of claim 9 , further comprising enabling a global sense amplifier coupled to the first and second global bit lines after developing the global read voltage on the second global bit line, whereby the global sense amplifier drives the first global bit line to the first supply voltage and the second global bit line to the second supply voltage in response to the global read voltage on the second global bit line.
11. A method of accessing a dynamic random access memory (DRAM) cell comprising:
driving a first bit line to a first pre-charge voltage and driving a second bit line to a second pre-charge voltage, wherein the first pre-charge voltage is different than the second pre-charge voltage; then
ceasing to drive the first bit line to the first pre-charge voltage, and enabling a DRAM cell coupled to the first bit line, thereby developing a read voltage on the first bit line;
continuing to drive the second bit line to the second pre-charge voltage while the read voltage is developing on the first bit line; and then
ceasing to drive the second bit line to the second pre-charge voltage, and enabling a sense amplifier coupled to the first and second bit lines, whereby the sense amplifier drives the first bit line to a first supply voltage and the second bit line to a second supply voltage in response to the read voltage on the first bit line.
12. The method of claim 11 , wherein the step of driving the first and second bit lines to the pre-charge voltage comprises:
driving a first global bit line to the first pre-charge voltage, and electrically connecting the first global bit line to the first bit line: and
driving a second global bit line to the second pre-charge voltage, and electrically connecting the second global bit line to the second bit line.
13. The method of claim 12 , wherein the step of ceasing to drive the first bit line to the first pre-charge voltage comprises electrically isolating the first bit line from the first global bit line.
14. The method of claim 13 , wherein the step of ceasing to drive the second bit line to the second pre-charge voltage comprises electrically isolating the second bit line from the second global bit line.
15. The method of claim 12 , further comprising:
charging the first and second global bit lines to the second pre-charge voltage after enabling the sense amplifier; then
coupling the second bit line to the second global bit line, thereby developing a global read voltage on the second global bit line; and
electrically isolating the first bit line from the first global bit line while the global read voltage is developed on the second global bit line.
16. The method of claim 15 , further comprising enabling a global sense amplifier coupled to the first and second global bit lines after developing the global read voltage on the second global bit line.
17. The method of claim 16 , wherein the global read voltage developed on the second global bit line is equal to the first pre-charge voltage.
18. The method of claim 11 , wherein the first pre-charge voltage is equal to one of the first and second supply voltages, and the second pre-charge voltage is between the first supply voltage and the second supply voltage.
19. The method of claim 12 , further comprising:
electrically isolating the first and second global bit lines from the first and second pre-charge voltages after enabling the sense amplifier; and then
coupling the first bit line to the first global bit line, thereby developing a global read voltage on the first global bit line.
20. The method of claim 19 , further comprising enabling a global sense amplifier coupled to the first and second global bit lines after developing the global read voltage on the first global bit line.
21. The method of claim 19 , wherein the global read voltage developed on the first global bit line is equal to the first pre-charge voltage.
22. The method of claim 19 , wherein the global read voltage developed on the first global bit line is less than the second pre-charge voltage.