Hierarchical multi-bank multi-port memory organization
View Patent ↗A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.
1. A memory system comprising:
a first plurality of ports, including one or more read ports and one or more write ports, wherein each of the first plurality of ports includes a corresponding address bus for providing a corresponding address; and
a first plurality of memory banks, each including a corresponding array of single port memory cells and a corresponding access control circuit,
wherein each access control circuit is coupled to each of the address buses of the first plurality of ports,
wherein each access control circuit is coupled to receive each of the addresses provided on each of the address buses, and
in response to these received addresses,
determines whether any of the first plurality of ports address the corresponding memory bank, and
initiates a read operation to the corresponding array of single port memory cells in response to determining that one of the one or more read ports addresses the corresponding memory bank, and
initiates a write operation to the corresponding array of single port memory cells in response to determining that one of the one or more write ports addresses the corresponding memory bank.
2. The memory system of claim 1 , wherein the number of memory banks in the first plurality of memory banks is greater than or equal to the number of ports in the first plurality of ports.
3. The memory system of claim 1 , wherein the first plurality of ports comprises a first read port for initiating read accesses to the first plurality of memory banks, a second read port for initiating read accesses to the first plurality of memory banks, and a write port for initiating write accesses to the first plurality of memory banks.
4. A memory system comprising:
a first plurality of ports, including one or more read ports and one or more write ports, wherein each of the first plurality of ports includes a corresponding address bus; and
a first plurality of memory banks, each including a corresponding array of single port memory cells, a corresponding access control circuit, and a multiplexer having inputs coupled to receive an access address from each of the first plurality of ports, and an output that provides one of the received access addresses to the corresponding array of single port memory cells,
wherein each access control circuit is coupled to the address buses of the first plurality of ports,
wherein each access control circuit is coupled to receive addresses provided on each of the address buses, and
in response to these received addresses,
determines whether any of the first plurality of ports address the corresponding memory bank, and
initiates a read operation to the corresponding array of single port memory cells in response to determining that one of the one or more read ports addresses the corresponding memory bank, and
initiates a write operation to the corresponding array of single port memory cells in response to determining that one of the one or more write ports addresses the corresponding memory bank.
5. The memory system of claim 1 , wherein the first plurality of ports includes a plurality of read ports, and wherein each of the first plurality of memory banks further comprises a de-multiplexer having an input coupled to receive a read data value from the corresponding array of single port memory cells, and a plurality of outputs, each coupled to a corresponding one of the plurality of read ports.
6. The memory system of claim 1 , further comprising:
a second plurality of ports, including one or more read ports and one or more write ports; and
a second plurality of memory banks, each including a corresponding array of single port memory cells and a corresponding access control circuit, wherein each access control circuit of the second plurality of memory banks is coupled to each of the second plurality of ports, wherein each access control circuit of the second plurality of memory banks determines whether any of the second plurality of ports address the corresponding memory bank, and initiates a read operation to the corresponding array of single port memory cells in response to determining that one of the one or more read ports of the second plurality of ports addresses the corresponding memory bank, and initiates a write operation to the corresponding array of single port memory cells in response to determining that one of the one or more write ports of the second plurality of ports addresses the corresponding memory bank.
7. The memory system of claim 6 , wherein the first plurality of ports are mutually exclusive of the second plurality of ports.
8. The memory system of claim 7 , wherein the first plurality of memory banks are mutually exclusive of the second plurality of memory banks.
9. The memory system of claim 1 , wherein each of the first plurality of ports comprises a data bus and an address bus, separate from the data bus.
10. The memory system of claim 4 , wherein the number of memory banks in the first plurality of memory banks is greater than or equal to the number of ports in the first plurality of ports.
11. The memory system of claim 4 , wherein the first plurality of ports comprises a first read port for initiating read accesses to the first plurality of memory banks, a second read port for initiating read accesses to the first plurality of memory banks, and a write port for initiating write accesses to the first plurality of memory banks.
12. The memory system of claim 4 , wherein the first plurality of ports includes a plurality of read ports, and wherein each of the first plurality of memory banks further comprises a de-multiplexer having an input coupled to receive a read data value from the corresponding array of single port memory cells, and a plurality of outputs, each coupled to a corresponding one of the plurality of read ports.
13. The memory system of claim 4 , further comprising:
a second plurality of ports, including one or more read ports and one or more write ports; and
a second plurality of memory banks, each including a corresponding array of single port memory cells and a corresponding access control circuit, wherein each access control circuit of the second plurality of memory banks is coupled to each of the second plurality of ports, wherein each access control circuit of the second plurality of memory banks determines whether any of the second plurality of ports address the corresponding memory bank, and initiates a read operation to the corresponding array of single port memory cells in response to determining that one of the one or more read ports of the second plurality of ports addresses the corresponding memory bank, and initiates a write operation to the corresponding array of single port memory cells in response to determining that one of the one or more write ports of the second plurality of ports addresses the corresponding memory bank.
14. The memory system of claim 13 , wherein the first plurality of ports are mutually exclusive of the second plurality of ports.
15. The memory system of claim 14 , wherein the first plurality of memory banks are mutually exclusive of the second plurality of memory banks.
16. The memory system of claim 4 , wherein each of the first plurality of ports comprises a data bus and an address bus, separate from the data bus.