Multiple cycle memory write completion
View Patent ↗A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.
1. A method of operating a memory system having a plurality of memory banks comprising:
performing an incomplete write operation of a first data value to a first address location in a first memory bank during a first memory cycle, wherein the incomplete write operation fails to pull a storage node of a memory cell at the first address location all the way to a first voltage associated with a first data state; and
performing a write operation of the first data value to a first address location in a cache memory during the first memory cycle.
2. The method of claim 1 , further comprising:
determining that there are no required accesses to the first memory bank during a second memory cycle; and
retrieving the first data value from the cache memory and writing this retrieved first data value to the first address location in the first memory bank during the second memory cycle.
3. The method of claim 2 , further comprising
performing an incomplete write operation of a second data value to a second address location in a second memory bank during a second memory cycle; and
performing a write operation of the second data value to a second address location in the cache memory during the second memory cycle.
4. The method of claim 2 , further comprising reading the first data value from the first address location in the cache memory during the second memory cycle.
5. The method of claim 2 , further comprising reading a second data value from a second memory bank during the second memory cycle.
6. The method of claim 1 , further comprising:
performing an incomplete write operation of a second data value to a second address location in the first memory bank during a second memory cycle, wherein the incomplete write operation fails to pull a storage node of a memory cell at the second address location all the way to the first voltage associated with the first data state; and
performing a write operation of the second data value to a second address location in the cache memory during the second memory cycle.